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Test and correct SUBs.

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This commit is contained in:
Thomas Harte 2022-04-19 16:27:20 -04:00
parent bfa551ec08
commit 76d7e0e1f8
2 changed files with 27 additions and 13 deletions
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29
InstructionSets/68k/Decoder.cpp
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@ -129,7 +129,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
// case EORIb: case EORIl: case EORIw: // case EORIb: case EORIl: case EORIw:
// case ORIb: case ORIl: case ORIw: // case ORIb: case ORIl: case ORIw:
// case ANDIb: case ANDIl: case ANDIw: // case ANDIb: case ANDIl: case ANDIw:
// case SUBIb: case SUBIl: case SUBIw: case SUBIb: case SUBIl: case SUBIw:
case ADDIb: case ADDIl: case ADDIw: case ADDIb: case ADDIl: case ADDIw:
// case CMPIb: case CMPIl: case CMPIw: // case CMPIb: case CMPIl: case CMPIw:
switch(original.mode<1>()) { switch(original.mode<1>()) {
@ -145,10 +145,11 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
// ADD. // ADD.
case OpT(Operation::ADDb): case OpT(Operation::ADDw): case OpT(Operation::ADDl): case OpT(Operation::ADDb): case OpT(Operation::ADDw): case OpT(Operation::ADDl):
case OpT(Operation::SUBb): case OpT(Operation::SUBw): case OpT(Operation::SUBl):
switch(original.mode<0>()) { switch(original.mode<0>()) {
default: break; default: break;
case AddressingMode::AddressRegisterDirect: case AddressingMode::AddressRegisterDirect:
if constexpr (op != OpT(Operation::ADDb)) { if constexpr (op != OpT(Operation::ADDb) && op != OpT(Operation::SUBb)) {
break; break;
} }
case AddressingMode::None: case AddressingMode::None:
@ -167,6 +168,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
// ADDA. // ADDA.
case OpT(Operation::ADDAw): case OpT(Operation::ADDAl): case OpT(Operation::ADDAw): case OpT(Operation::ADDAl):
case OpT(Operation::SUBAw): case OpT(Operation::SUBAl):
switch(original.mode<0>()) { switch(original.mode<0>()) {
default: break; default: break;
case AddressingMode::None: case AddressingMode::None:
@ -210,7 +212,8 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
// b3: 1 => operation is memory-to-memory; 0 => register-to-register. // b3: 1 => operation is memory-to-memory; 0 => register-to-register.
// //
case OpT(Operation::ABCD): case OpT(Operation::SBCD): case OpT(Operation::ABCD): case OpT(Operation::SBCD):
case OpT(Operation::ADDXb): case OpT(Operation::ADDXw): case OpT(Operation::ADDXl): { case OpT(Operation::ADDXb): case OpT(Operation::ADDXw): case OpT(Operation::ADDXl):
case OpT(Operation::SUBXb): case OpT(Operation::SUBXw): case OpT(Operation::SUBXl): {
const auto addressing_mode = (instruction & 8) ? const auto addressing_mode = (instruction & 8) ?
AddressingMode::AddressRegisterIndirectWithPredecrement : AddressingMode::DataRegisterDirect; AddressingMode::AddressRegisterIndirectWithPredecrement : AddressingMode::DataRegisterDirect;
@ -894,11 +897,11 @@ template <Model model>
Preinstruction Predecoder<model>::decode9(uint16_t instruction) { Preinstruction Predecoder<model>::decode9(uint16_t instruction) {
using Op = Operation; using Op = Operation;
switch(instruction & 0x0c0) { switch(instruction & 0x1f0) {
// 4-174 (p278) // 4-184 (p288)
case 0x00: Decode(Op::SUBb); case 0x100: Decode(Op::SUBXb);
case 0x40: Decode(Op::SUBw); case 0x140: Decode(Op::SUBXw);
case 0x80: Decode(Op::SUBl); case 0x180: Decode(Op::SUBXl);
default: break; default: break;
} }
@ -911,11 +914,11 @@ Preinstruction Predecoder<model>::decode9(uint16_t instruction) {
default: break; default: break;
} }
switch(instruction & 0x1f0) { switch(instruction & 0x0c0) {
// 4-184 (p288) // 4-174 (p278)
case 0x100: Decode(Op::SUBXb); case 0x00: Decode(Op::SUBb);
case 0x140: Decode(Op::SUBXw); case 0x40: Decode(Op::SUBw);
case 0x180: Decode(Op::SUBXl); case 0x80: Decode(Op::SUBl);
default: break; default: break;
} }

11
OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm
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@ -101,6 +101,17 @@ template <int index> NSString *operand(Preinstruction instruction) {
case Operation::ADDXw: instruction = @"ADDX.w"; break; case Operation::ADDXw: instruction = @"ADDX.w"; break;
case Operation::ADDXl: instruction = @"ADDX.l"; break; case Operation::ADDXl: instruction = @"ADDX.l"; break;
case Operation::SUBb: instruction = @"SUB.b"; break;
case Operation::SUBw: instruction = @"SUB.w"; break;
case Operation::SUBl: instruction = @"SUB.l"; break;
case Operation::SUBAw: instruction = @"SUBA.w"; break;
case Operation::SUBAl: instruction = @"SUBA.l"; break;
case Operation::SUBXb: instruction = @"SUBX.b"; break;
case Operation::SUBXw: instruction = @"SUBX.w"; break;
case Operation::SUBXl: instruction = @"SUBX.l"; break;
// For now, skip any unmapped operations. // For now, skip any unmapped operations.
default: continue; default: continue;
} }