diff --git a/Processors/68000/Implementation/68000Implementation.hpp b/Processors/68000/Implementation/68000Implementation.hpp
index b7ed9827f..0eee95437 100644
--- a/Processors/68000/Implementation/68000Implementation.hpp
+++ b/Processors/68000/Implementation/68000Implementation.hpp
@@ -261,6 +261,13 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
 #endif
 
 							decoded_instruction_.full = prefetch_queue_.halves.high.full;
+
+#ifndef NDEBUG
+							/* Debugging feature: reset the effective addresses and data latches, so that it's
+							more obvious if some of the instructions aren't properly feeding them. */
+							effective_address_[0].full = effective_address_[1].full = source_bus_data_[0].full = destination_bus_data_[0].full = 0x12344321;
+#endif
+
 #ifdef LOG_TRACE
 							if(should_log) {
 								std::cout << std::hex << (program_counter_.full - 4) << ": " << std::setw(4) << decoded_instruction_.full << '\t';
@@ -272,7 +279,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
 							}
 
 #ifdef LOG_TRACE
-							should_log |= ((program_counter_.full - 4) == 0x40103e);
+							should_log |= ((program_counter_.full - 4) == 0x4058dc);	// 0x40103e
 #endif
 
 							if(instructions[decoded_instruction_.full].micro_operations) {
diff --git a/Processors/68000/Implementation/68000Storage.cpp b/Processors/68000/Implementation/68000Storage.cpp
index 8581c1fb4..e2afad2a5 100644
--- a/Processors/68000/Implementation/68000Storage.cpp
+++ b/Processors/68000/Implementation/68000Storage.cpp
@@ -2407,6 +2407,7 @@ struct ProcessorStorageConstructor {
 
 								case XXXl:		// PEA (XXX).l
 								case XXXw:		// PEA (XXX).w
+									storage_.instructions[instruction].source = &storage_.effective_address_[0];
 									op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, (mode == XXXl) ? seq("np") : nullptr);
 									op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
 									op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
@@ -2416,6 +2417,7 @@ struct ProcessorStorageConstructor {
 								case d16PC:		// PEA (d16, PC)
 								case d8AnXn:	// PEA (d8, An, Xn)
 								case d8PCXn:	// PEA (d8, PC, Xn)
+									storage_.instructions[instruction].source = &storage_.effective_address_[0];
 									op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask);
 									op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np", mode)));
 									op(Action::PerformOperation, seq(pseq("np nW+ nw", mode), { ea(1), ea(1) }));