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Consolidate BCLR, BCHG and BSET into a macro.
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@ -88,6 +88,24 @@ static void add_sub(IntT source, IntT &destination, Status &status) {
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destination = result;
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}
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inline uint32_t mask_bit(const Preinstruction &instruction, uint32_t source) {
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return source & (instruction.mode<1>() == AddressingMode::DataRegisterDirect ? 31 : 7);
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}
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template <Operation operation, typename FlowController>
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void bit_manipulate(const Preinstruction &instruction, uint32_t source, uint32_t &destination, Status &status, FlowController &flow_controller) {
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static_assert(operation == Operation::BCLR || operation == Operation::BCHG || operation == Operation::BSET);
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const auto bit = mask_bit(instruction, source);
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status.zero_result = destination & (1 << bit);
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switch(operation) {
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case Operation::BCLR: destination &= ~(1 << bit); break;
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case Operation::BCHG: destination ^= (1 << bit); break;
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case Operation::BSET: destination |= (1 << bit); break;
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}
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flow_controller.did_bit_op(int(bit));
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}
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}
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template <
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@ -148,42 +166,13 @@ template <
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case Operation::SUBAw: dest.l -= u_extend16(src.w); break;
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case Operation::SUBAl: dest.l -= src.l; break;
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#define get_mask() \
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const uint32_t mask_size = (instruction.mode<1>() == AddressingMode::DataRegisterDirect) ? 31 : 7; \
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const uint32_t bit_position = src.l & mask_size; \
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const uint32_t bit_mask = 1 << bit_position
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// BTST/BCLR/etc: modulo for the mask depends on whether memory or a data register is the target.
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case Operation::BTST: {
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get_mask();
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status.zero_result = dest.l & bit_mask;
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} break;
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case Operation::BCLR: {
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get_mask();
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status.zero_result = dest.l & bit_mask;
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dest.l &= ~bit_mask;
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flow_controller.did_bit_op(int(bit_position));
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} break;
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case Operation::BCHG: {
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get_mask();
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status.zero_result = dest.l & bit_mask;
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dest.l ^= bit_mask;
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flow_controller.did_bit_op(int(bit_position));
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} break;
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case Operation::BSET: {
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get_mask();
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status.zero_result = dest.l & bit_mask;
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dest.l |= bit_mask;
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flow_controller.did_bit_op(int(bit_position));
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} break;
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#undef get_mask
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case Operation::BTST:
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status.zero_result = dest.l & (1 << Primitive::mask_bit(instruction, src.l));
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break;
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case Operation::BCLR: Primitive::bit_manipulate<Operation::BCLR>(instruction, src.l, dest.l, status, flow_controller); break;
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case Operation::BCHG: Primitive::bit_manipulate<Operation::BCHG>(instruction, src.l, dest.l, status, flow_controller); break;
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case Operation::BSET: Primitive::bit_manipulate<Operation::BSET>(instruction, src.l, dest.l, status, flow_controller); break;
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case Operation::Bccb:
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flow_controller.template complete_bcc<int8_t>(
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