From 77bdaf3c7824abd89227e621787f25652bfd0f9e Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 21 Mar 2022 10:41:17 -0400 Subject: [PATCH] These are likely to be useful outside of the decoder. --- InstructionSets/PowerPC/Decoder.cpp | 8 ++++---- InstructionSets/PowerPC/Decoder.hpp | 24 ++++++++++++------------ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/InstructionSets/PowerPC/Decoder.cpp b/InstructionSets/PowerPC/Decoder.cpp index 1978994ea..611947e3d 100644 --- a/InstructionSets/PowerPC/Decoder.cpp +++ b/InstructionSets/PowerPC/Decoder.cpp @@ -36,11 +36,11 @@ Instruction Decoder::decode(uint32_t opcode) { #define BindSupervisor(mask, operation) case mask: return Instruction(Operation::operation, opcode, true); #define BindConditional(condition, mask, operation) \ case mask: \ - if(condition()) return Instruction(Operation::operation, opcode); \ + if(condition(model_)) return Instruction(Operation::operation, opcode); \ return Instruction(opcode); #define BindSupervisorConditional(condition, mask, operation) \ case mask: \ - if(condition()) return Instruction(Operation::operation, opcode, true); \ + if(condition(model_)) return Instruction(Operation::operation, opcode, true); \ return Instruction(opcode); #define Six(x) (unsigned(x) << 26) @@ -320,7 +320,7 @@ Instruction Decoder::decode(uint32_t opcode) { switch(opcode & 0b111111'00'00000000'000'111111111'1){ case 0b011111'00'00000000'00000'0010010110'1: return Instruction(Operation::stwcx_, opcode); case 0b011111'00'00000000'00000'0011010110'1: - if(is64bit()) return Instruction(Operation::stdcx_, opcode); + if(is64bit(model_)) return Instruction(Operation::stdcx_, opcode); return Instruction(opcode); } @@ -328,7 +328,7 @@ Instruction Decoder::decode(uint32_t opcode) { switch(opcode & 0b111111'00'00000000'00000000'000000'11){ case 0b111110'00'00000000'00000000'000000'00: return Instruction(Operation::std, opcode); case 0b111110'00'00000000'00000000'000000'01: - if(is64bit()) return Instruction(Operation::stdu, opcode); + if(is64bit(model_)) return Instruction(Operation::stdu, opcode); return Instruction(opcode); } diff --git a/InstructionSets/PowerPC/Decoder.hpp b/InstructionSets/PowerPC/Decoder.hpp index 5b1003a66..389ec40d3 100644 --- a/InstructionSets/PowerPC/Decoder.hpp +++ b/InstructionSets/PowerPC/Decoder.hpp @@ -23,6 +23,18 @@ enum class Model { MPC620, }; +constexpr bool is64bit(Model model) { + return model == Model::MPC620; +} + +constexpr bool is32bit(Model model) { + return !is64bit(model); +} + +constexpr bool is601(Model model) { + return model == Model::MPC601; +} + /*! Implements PowerPC instruction decoding. @@ -36,18 +48,6 @@ struct Decoder { private: Model model_; - - bool is64bit() const { - return model_ == Model::MPC620; - } - - bool is32bit() const { - return !is64bit(); - } - - bool is601() const { - return model_ == Model::MPC601; - } }; }