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Flattens the Macintosh's perform_bus_operation, for legibility.
This commit is contained in:
Thomas Harte
parent
69b94719a1
commit
7886cd63bd
@ -137,6 +137,9 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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using Microcycle = CPU::MC68000::Microcycle;
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HalfCycles perform_bus_operation(const Microcycle &cycle, int is_supervisor) {
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// TODO: pick a delay if this is a video-clashing memory fetch.
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HalfCycles delay(0);
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time_since_video_update_ += cycle.length;
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iwm_.time_since_update += cycle.length;
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@ -209,167 +212,152 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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} else {
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mc68000_.set_interrupt_level(0);
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}
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// mc68000_.set_interrupt_level(
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// (via_.get_interrupt_line() ? 1 : 0) |
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// (scc_.get_interrupt_line() ? 2 : 0)
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// /* TODO: to emulate a programmer's switch: have it set bit 2 when pressed. */
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// );
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// A null cycle leaves nothing else to do.
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if(cycle.operation) {
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auto word_address = cycle.word_address();
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if(!cycle.operation) return delay;
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// Everything above E0 0000 is signalled as being on the peripheral bus.
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mc68000_.set_is_peripheral_address(word_address >= 0x700000);
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auto word_address = cycle.word_address();
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if(word_address >= 0x400000) {
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if(cycle.data_select_active()) {
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const int register_address = word_address >> 8;
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// Everything above E0 0000 is signalled as being on the peripheral bus.
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mc68000_.set_is_peripheral_address(word_address >= 0x700000);
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switch(word_address & 0x78f000) {
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case 0x70f000:
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// VIA accesses are via address 0xefe1fe + register*512,
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// which at word precision is 0x77f0ff + register*256.
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = via_.get_register(register_address);
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// All code below deals only with reads and writes — cycles in which a
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// data select is active. So quit now if this is not the active part of
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// a read or write.
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if(!cycle.data_select_active()) return delay;
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// Check whether this access maps into the IO area; if so then
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// apply more complicated decoding logic.
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if(word_address >= 0x400000) {
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const int register_address = word_address >> 8;
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switch(word_address & 0x78f000) {
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case 0x70f000:
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// VIA accesses are via address 0xefe1fe + register*512,
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// which at word precision is 0x77f0ff + register*256.
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = via_.get_register(register_address);
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} else {
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via_.set_register(register_address, cycle.value->halves.low);
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}
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break;
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case 0x68f000:
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// The IWM; this is a purely polled device, so can be run on demand.
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iwm_.flush();
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = iwm_.iwm.read(register_address);
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} else {
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iwm_.iwm.write(register_address, cycle.value->halves.low);
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}
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break;
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case 0x780000:
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// Phase read.
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = phase_ & 7;
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}
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break;
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case 0x480000: case 0x48f000:
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case 0x580000: case 0x58f000:
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// Any word access here adjusts phase.
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if(cycle.operation & Microcycle::SelectWord) {
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++phase_;
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} else {
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if(word_address < 0x500000) {
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// A0 = 1 => reset; A0 = 0 => read.
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if(*cycle.address & 1) {
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scc_.reset();
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} else {
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via_.set_register(register_address, cycle.value->halves.low);
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}
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break;
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case 0x68f000:
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// The IWM; this is a purely polled device, so can be run on demand.
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#ifndef NDEBUG
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// printf("[%06x]: ", mc68000_.get_state().program_counter);
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#endif
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iwm_.flush();
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = iwm_.iwm.read(register_address);
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} else {
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iwm_.iwm.write(register_address, cycle.value->halves.low);
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}
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break;
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case 0x780000:
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// Phase read.
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = phase_ & 7;
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}
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break;
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case 0x480000: case 0x48f000:
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case 0x580000: case 0x58f000:
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// Any word access here adjusts phase.
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if(cycle.operation & Microcycle::SelectWord) {
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++phase_;
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} else {
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if(word_address < 0x500000) {
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// A0 = 1 => reset; A0 = 0 => read.
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if(*cycle.address & 1) {
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scc_.reset();
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} else {
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const auto read = scc_.read(int(word_address));
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = read;
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}
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}
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} else {
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if(*cycle.address & 1) {
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if(cycle.operation & Microcycle::Read) {
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scc_.write(int(word_address), 0xff);
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} else {
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scc_.write(int(word_address), cycle.value->halves.low);
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}
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}
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const auto read = scc_.read(int(word_address));
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = read;
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}
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}
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break;
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default:
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if(cycle.operation & Microcycle::Read) {
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printf("Unrecognised read %06x\n", *cycle.address & 0xffffff);
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cycle.value->halves.low = 0x00;
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} else {
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printf("Unrecognised write %06x\n", *cycle.address & 0xffffff);
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} else {
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if(*cycle.address & 1) {
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if(cycle.operation & Microcycle::Read) {
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scc_.write(int(word_address), 0xff);
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} else {
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scc_.write(int(word_address), cycle.value->halves.low);
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}
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}
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break;
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}
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}
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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}
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} else {
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if(cycle.data_select_active()) {
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uint16_t *memory_base = nullptr;
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auto operation = cycle.operation;
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break;
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// When ROM overlay is enabled, the ROM begins at both $000000 and $400000,
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// and RAM is available at $600000.
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//
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// Otherwise RAM is mapped at $000000 and ROM from $400000.
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if(
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(ROM_is_overlay_ && word_address >= 0x300000) ||
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(!ROM_is_overlay_ && word_address < 0x200000)
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) {
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memory_base = ram_;
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word_address &= ram_mask_;
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update_video();
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default:
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if(cycle.operation & Microcycle::Read) {
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printf("Unrecognised read %06x\n", *cycle.address & 0xffffff);
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cycle.value->halves.low = 0x00;
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} else {
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memory_base = rom_;
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word_address &= rom_mask_;
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// Disallow writes to ROM; also it doesn't mirror above 0x60000, ever.
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if(!(operation & Microcycle::Read) || word_address >= 0x300000) operation = 0;
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printf("Unrecognised write %06x\n", *cycle.address & 0xffffff);
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}
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const auto masked_operation = operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge);
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switch(masked_operation) {
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default:
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break;
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// Catches the deliberation set of operation to 0 above.
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case 0: break;
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case Microcycle::InterruptAcknowledge | Microcycle::SelectByte:
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// The Macintosh uses autovectored interrupts.
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mc68000_.set_is_peripheral_address(true);
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break;
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = memory_base[word_address];
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = uint8_t(memory_base[word_address] >> cycle.byte_shift());
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break;
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case Microcycle::SelectWord:
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memory_base[word_address] = cycle.value->full;
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break;
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case Microcycle::SelectByte:
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memory_base[word_address] = uint16_t(
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(cycle.value->halves.low << cycle.byte_shift()) |
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(memory_base[word_address] & cycle.untouched_byte_mask())
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);
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break;
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}
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// if(!(operation & Microcycle::Read) && (word_address == (0x00000172 >> 1))) {
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// if(operation & Microcycle::SelectByte)
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// printf("MBState: %02x\n", cycle.value->halves.low);
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// else
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// printf("MBState: %04x\n", cycle.value->full);
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// }
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// if(
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// (
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// (word_address == (0x00000352 >> 1))
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// || (word_address == (0x00000354 >> 1))
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// || (word_address == (0x00005d16 >> 1))
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// )
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// ) {
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// printf("%s %08x: %04x from around %08x\n", (operation & Microcycle::Read) ? "Read" : "Write", word_address << 1, memory_base[word_address], mc68000_.get_state().program_counter);
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// }
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} else {
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// TODO: add delay if this is a RAM access and video blocks it momentarily.
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// "Each [video] fetch took two cycles out of eight"
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}
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break;
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}
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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return delay;
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}
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// Having reached here, this is a RAM or ROM access.
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// When ROM overlay is enabled, the ROM begins at both $000000 and $400000,
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// and RAM is available at $600000.
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//
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// Otherwise RAM is mapped at $000000 and ROM from $400000.
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uint16_t *memory_base;
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if(
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(!ROM_is_overlay_ && word_address < 0x200000) ||
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(ROM_is_overlay_ && word_address >= 0x300000)
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) {
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memory_base = ram_;
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word_address &= ram_mask_;
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update_video();
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} else {
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memory_base = rom_;
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word_address &= rom_mask_;
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// Writes to ROM have no effect, and it doesn't mirror above 0x60000.
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if(!(cycle.operation & Microcycle::Read)) return delay;
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if(word_address >= 0x300000) {
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if(cycle.operation & Microcycle::SelectWord) {
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cycle.value->full = 0xffff;
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} else {
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cycle.value->halves.low = 0xff;
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}
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return delay;
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}
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}
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge)) {
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default:
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break;
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// Catches the deliberation set of operation to 0 above.
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case 0: break;
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case Microcycle::InterruptAcknowledge | Microcycle::SelectByte:
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// The Macintosh uses autovectored interrupts.
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mc68000_.set_is_peripheral_address(true);
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break;
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = memory_base[word_address];
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = uint8_t(memory_base[word_address] >> cycle.byte_shift());
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break;
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case Microcycle::SelectWord:
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memory_base[word_address] = cycle.value->full;
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break;
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case Microcycle::SelectByte:
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memory_base[word_address] = uint16_t(
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(cycle.value->halves.low << cycle.byte_shift()) |
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(memory_base[word_address] & cycle.untouched_byte_mask())
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);
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break;
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}
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/*
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@ -383,7 +371,7 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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EFE1FE+: VIA
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*/
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return HalfCycles(0);
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return delay;
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}
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void flush() {
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