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Moves contention delays up to the time of MREQ going active.
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@ -141,36 +141,35 @@ template<Model model> class ConcreteMachine:
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// MARK: - BusHandler
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forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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// Ignore all but terminal cycles.
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// TODO: I doubt this is correct for timing.
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if(!cycle.is_terminal()) {
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advance(cycle.length);
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return HalfCycles(0);
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}
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using PartialMachineCycle = CPU::Z80::PartialMachineCycle;
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HalfCycles delay(0);
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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using PartialMachineCycle = CPU::Z80::PartialMachineCycle;
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const uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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default: break;
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case PartialMachineCycle::ReadOpcodeStart:
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case PartialMachineCycle::ReadStart:
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case PartialMachineCycle::WriteStart:
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// Apply contention if necessary.
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// For now this causes a video sync up every time any contended area is written to.
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// TODO: flush only upon a video-area write.
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//
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// Assumption here: the trigger for the ULA inserting a delay is the falling edge
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// of MREQ, which is always half a cycle into a read or write.
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//
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// TODO: somehow provide that information in the PartialMachineCycle?
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if(is_contended_[address >> 14]) {
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delay = video_->access_delay(HalfCycles(1));
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}
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break;
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case PartialMachineCycle::ReadOpcode:
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case PartialMachineCycle::Read:
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// Apply contention if necessary.
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if(is_contended_[address >> 14]) {
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delay = video_.last_valid()->access_delay(video_.time_since_flush());
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}
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*cycle.value = read_pointers_[address >> 14][address];
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break;
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case PartialMachineCycle::Write:
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// Apply contention if necessary.
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// For now this causes a video sync up every time any contended area is written to.
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// TODO: flush only upon a video-area write.
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if(is_contended_[address >> 14]) {
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delay = video_->access_delay(HalfCycles(0));
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}
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write_pointers_[address >> 14][address] = *cycle.value;
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break;
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