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https://github.com/TomHarte/CLK.git
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This is the start of my slog through type 1 commands. I kind of need to figure out what I'm doing about drives and PLLs now though.
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@ -67,8 +67,102 @@ void WD1770::run_for_cycles(unsigned int number_of_cycles)
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}
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}
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continue;
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continue;
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case State::BeginType1:
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status_ |= Flag::Busy;
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status_ &= ~(Flag::DataRequest | Flag::CRCError);
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set_interrupt_request(false);
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state_ = State::BeginType1PostSpin;
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if(command_ & 0x08)
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{
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wait_six_index_pulses_.next_state = state_;
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wait_six_index_pulses_.count = 0;
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state_ = State::WaitForSixIndexPulses;
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}
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continue;
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// case State::WaitForSixIndexPulses:
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// continue;
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case State::BeginType1PostSpin:
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switch(command_ >> 4)
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{
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case 0: // restore
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track_ = 0xff; // deliberate fallthrough
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case 1: // seek
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data_ = 0x00;
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break;
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case 2: case 3: // step
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break;
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case 4: case 5: // step in
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is_step_in_ = true;
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break;
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case 6: case 7: // step out
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is_step_in_ = false;
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break;
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}
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if(!(command_ >> 5))
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state_ = State::TestTrack;
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else
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state_ = (command_ & 0x10) ? State::TestDirection : State::TestHead;
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continue;
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case State::TestTrack:
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data_shift_register_ = data_;
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if(track_ == data_shift_register_)
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state_ = State::TestVerify;
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else
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{
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is_step_in_ = (data_shift_register_ < track_);
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state_ = State::TestDirection;
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}
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continue;
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case State::TestDirection:
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track_ += is_step_in_ ? -1 : +1;
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state_ = State::TestHead;
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continue;
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// case State::TestHead:
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// break;
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case State::TestVerify:
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if(command_ & 0x04)
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{
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state_ = State::VerifyTrack;
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}
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else
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{
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set_interrupt_request(true);
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status_ &= ~Flag::Busy;
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state_ = State::Waiting;
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}
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break;
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// +------+----------+-------------------------+
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// ! ! ! BITS !
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// ! TYPE ! COMMAND ! 7 6 5 4 3 2 1 0 !
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// +------+----------+-------------------------+
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// ! 1 ! Restore ! 0 0 0 0 h v r1 r0 !
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// ! 1 ! Seek ! 0 0 0 1 h v r1 r0 !
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// ! 1 ! Step ! 0 0 1 u h v r1 r0 !
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// ! 1 ! Step-in ! 0 1 0 u h v r1 r0 !
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// ! 1 ! Step-out ! 0 1 1 u h v r1 r0 !
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// ! 2 ! Rd sectr ! 1 0 0 m h E 0 0 !
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// ! 2 ! Wt sectr ! 1 0 1 m h E P a0 !
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// ! 3 ! Rd addr ! 1 1 0 0 h E 0 0 !
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// ! 3 ! Rd track ! 1 1 1 0 h E 0 0 !
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// ! 3 ! Wt track ! 1 1 1 1 h E P 0 !
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// ! 4 ! Forc int ! 1 1 0 1 i3 i2 i1 i0 !
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// +------+----------+-------------------------+
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default:
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default:
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printf("Unhandled state %d!", state_);
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{
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static bool has_hit_error = false;
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if(!has_hit_error)
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printf("Unhandled state %d!\n", state_);
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has_hit_error = true;
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}
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return;
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return;
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}
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}
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}
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}
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@ -43,15 +43,30 @@ class WD1770 {
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enum class State {
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enum class State {
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Waiting,
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Waiting,
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BeginType1, BeginType2, BeginType3
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BeginType1, BeginType2, BeginType3,
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BeginType1PostSpin,
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WaitForSixIndexPulses,
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TestTrack, TestDirection, TestHead,
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TestVerify, VerifyTrack
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} state_;
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} state_;
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union {
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struct {
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int count;
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State next_state;
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} wait_six_index_pulses_;
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};
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uint8_t status_;
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uint8_t status_;
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uint8_t track_;
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uint8_t track_;
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uint8_t sector_;
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uint8_t sector_;
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uint8_t data_;
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uint8_t data_;
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uint8_t command_;
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uint8_t command_;
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bool has_command_;
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bool has_command_;
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void set_interrupt_request(bool interrupt_request) {}
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bool is_step_in_;
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uint8_t data_shift_register_;
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};
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};
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}
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}
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