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https://github.com/TomHarte/CLK.git
synced 2024-11-23 03:32:32 +00:00
[Re]discovered that sync may also be a product of the interrupt cycle. So started looking into that.
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@ -11,7 +11,8 @@
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using namespace ZX8081;
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Machine::Machine() :
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vertical_sync_(false),
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vsync_(false),
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hsync_(false),
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ram_(65536) {
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// run at 3.25 Mhz
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set_clock_rate(3250000);
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@ -23,24 +24,26 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
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uint8_t r;
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switch(cycle.operation) {
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case CPU::Z80::BusOperation::Output:
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if(*cycle.address == 0xff) {
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update_display();
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set_sync(false);
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if((*cycle.address&0xff) == 0xff) {
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set_vsync(false);
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}
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break;
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case CPU::Z80::BusOperation::Input:
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if(*cycle.address == 0xfe) {
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update_display();
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set_sync(true);
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if((*cycle.address&0xff) == 0xfe) {
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set_vsync(true);
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}
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*cycle.value = 0xff;
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break;
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case CPU::Z80::BusOperation::Interrupt:
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set_hsync(true);
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*cycle.value = 0xff;
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break;
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case CPU::Z80::BusOperation::ReadOpcode:
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set_hsync(false);
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// printf("%04x\n", *cycle.address);
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r = (uint8_t)get_value_of_register(CPU::Z80::Register::R);
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set_interrupt_line(!(r & 0x40));
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case CPU::Z80::BusOperation::Read:
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@ -113,8 +116,16 @@ void Machine::update_display() {
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cycles_since_display_update_ = 0;
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}
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void Machine::set_sync(bool sync) {
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void Machine::set_vsync(bool sync) {
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if(sync && !vsync_) printf("\n---\n");
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vsync_ = sync;
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}
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void Machine::set_hsync(bool sync) {
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if(sync && !hsync_) printf("\n");
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hsync_ = sync;
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}
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void Machine::output_byte(uint8_t byte) {
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printf("%02x ", byte);
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}
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@ -50,11 +50,12 @@ class Machine:
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std::vector<uint8_t> zx81_rom_, zx80_rom_, rom_;
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std::vector<uint8_t> ram_;
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bool vertical_sync_;
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bool vsync_, hsync_;
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int cycles_since_display_update_;
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void update_display();
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void set_sync(bool sync);
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void set_vsync(bool sync);
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void set_hsync(bool sync);
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void output_byte(uint8_t byte);
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};
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