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Default to ROM01.

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This commit is contained in:
Thomas Harte 2021-09-09 22:09:09 -04:00
parent a6221ca322
commit 7e5fc4444a
2 changed files with 6 additions and 1 deletions
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2
Analyser/Static/AppleIIgs/Target.hpp
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@ -29,7 +29,7 @@ struct Target: public Analyser::Static::Target, public Reflection::StructImpl<Ta
EightMB EightMB
); );
Model model = Model::ROM03; Model model = Model::ROM01;
MemoryModel memory_model = MemoryModel::EightMB; MemoryModel memory_model = MemoryModel::EightMB;
Target() : Analyser::Static::Target(Machine::AppleIIgs) { Target() : Analyser::Static::Target(Machine::AppleIIgs) {

5
Machines/Apple/AppleIIgs/AppleIIgs.cpp
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@ -277,6 +277,11 @@ class ConcreteMachine:
// std::srand(23); // std::srand(23);
Memory::Fuzz(ram_); Memory::Fuzz(ram_);
// Prior to ROM03 there's no power-on bit.
if(target.model != Target::Model::ROM03) {
speed_register_ &= ~0x40;
}
// Sync up initial values. // Sync up initial values.
memory_.set_speed_register(speed_register_ ^ 0x80); memory_.set_speed_register(speed_register_ ^ 0x80);