6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-25 16:31:42 +00:00
Code Issues Projects Releases Wiki Activity

Default to ROM01.

Browse Source
This commit is contained in:
Thomas Harte 2021-09-09 22:09:09 -04:00
parent a6221ca322
commit 7e5fc4444a
2 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Analyser/Static/AppleIIgs/Target.hpp
View File

@ -29,7 +29,7 @@ struct Target: public Analyser::Static::Target, public Reflection::StructImpl<Ta
EightMB
);
Model model = Model::ROM03;
Model model = Model::ROM01;
MemoryModel memory_model = MemoryModel::EightMB;
Target() : Analyser::Static::Target(Machine::AppleIIgs) {

5
Machines/Apple/AppleIIgs/AppleIIgs.cpp
View File

@ -277,6 +277,11 @@ class ConcreteMachine:
// std::srand(23);
Memory::Fuzz(ram_);
// Prior to ROM03 there's no power-on bit.
if(target.model != Target::Model::ROM03) {
speed_register_ &= ~0x40;
}
// Sync up initial values.
memory_.set_speed_register(speed_register_ ^ 0x80);