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Merge pull request #1036 from TomHarte/InMacintosh
Switch the Macintosh to the newer 68000.
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commit
7eb00c131f
@ -50,6 +50,7 @@
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namespace {
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constexpr int CLOCK_RATE = 7833600;
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constexpr auto KEYBOARD_CLOCK_RATE = HalfCycles(CLOCK_RATE / 100000);
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// Former default PRAM:
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@ -73,7 +74,7 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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public MachineTypes::MediaTarget,
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public MachineTypes::MouseMachine,
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public MachineTypes::MappedKeyboardMachine,
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public CPU::MC68000::BusHandler,
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public CPU::MC68000Mk2::BusHandler,
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public Zilog::SCC::z8530::Delegate,
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public Activity::Source,
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public Configurable::Device,
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@ -191,9 +192,9 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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mc68000_.run_for(cycles);
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}
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using Microcycle = CPU::MC68000::Microcycle;
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using Microcycle = CPU::MC68000Mk2::Microcycle;
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forceinline HalfCycles perform_bus_operation(const Microcycle &cycle, int) {
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HalfCycles perform_bus_operation(const Microcycle &cycle, int) {
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// Advance time.
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advance_time(cycle.length);
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@ -204,6 +205,10 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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auto address = cycle.host_endian_byte_address();
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// Everything above E0 0000 is signalled as being on the peripheral bus.
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//
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// This will also act to autovector interrupts, since an interrupt acknowledge
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// cycle posts an address with all the higher-order bits set, and VPA doubles
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// as the input to request an autovector.
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mc68000_.set_is_peripheral_address(address >= 0xe0'0000);
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// All code below deals only with reads and writes — cycles in which a
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@ -235,21 +240,17 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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// VIA accesses are via address 0xefe1fe + register*512,
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// which at word precision is 0x77f0ff + register*256.
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = via_.read(register_address);
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cycle.set_value8_high(via_.read(register_address));
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} else {
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via_.write(register_address, cycle.value->halves.low);
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via_.write(register_address, cycle.value8_high());
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}
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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}
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} return delay;
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case BusDevice::PhaseRead: {
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = phase_ & 7;
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cycle.set_value8_low(phase_ & 7);
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}
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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} return delay;
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case BusDevice::IWM: {
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@ -258,12 +259,10 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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// The IWM; this is a purely polled device, so can be run on demand.
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = iwm_->read(register_address);
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cycle.set_value8_low(iwm_->read(register_address));
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} else {
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iwm_->write(register_address, cycle.value->halves.low);
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iwm_->write(register_address, cycle.value8_low());
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}
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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} else {
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fill_unmapped(cycle);
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}
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@ -279,22 +278,12 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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if(cycle.operation & Microcycle::Read) {
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scsi_.write(register_address, 0xff, dma_acknowledge);
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} else {
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if(cycle.operation & Microcycle::SelectWord) {
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scsi_.write(register_address, cycle.value->halves.high, dma_acknowledge);
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} else {
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scsi_.write(register_address, cycle.value->halves.low, dma_acknowledge);
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}
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scsi_.write(register_address, cycle.value8_high());
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}
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} else {
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// Even access => this is a read.
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if(cycle.operation & Microcycle::Read) {
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const auto result = scsi_.read(register_address, dma_acknowledge);
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if(cycle.operation & Microcycle::SelectWord) {
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// Data is loaded on the top part of the bus only.
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cycle.value->full = uint16_t((result << 8) | 0xff);
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} else {
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cycle.value->halves.low = result;
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}
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cycle.set_value8_high(scsi_.read(register_address, dma_acknowledge));
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}
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}
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} return delay;
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@ -309,12 +298,12 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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scc_.reset();
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = 0xff;
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cycle.set_value16(0xffff);
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}
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} else {
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const auto read = scc_.read(int(address >> 1));
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = read;
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cycle.set_value8_high(read);
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}
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}
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}
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@ -325,12 +314,14 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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if(cycle.operation & Microcycle::SelectWord) {
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adjust_phase();
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} else {
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// This is definitely a byte access; either it's to an odd address, in which
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// case it will reach the SCC, or it isn't, in which case it won't.
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if(*cycle.address & 1) {
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if(cycle.operation & Microcycle::Read) {
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scc_.write(int(address >> 1), 0xff);
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cycle.value->halves.low = 0xff;
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cycle.value->b = 0xff;
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} else {
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scc_.write(int(address >> 1), cycle.value->halves.low);
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scc_.write(int(address >> 1), cycle.value->b);
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}
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} else {
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fill_unmapped(cycle);
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@ -368,23 +359,8 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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}
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// If control has fallen through to here, the access is either a read from ROM, or a read or write to RAM.
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
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default:
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break;
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = *reinterpret_cast<uint16_t *>(&memory_base[address]);
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = memory_base[address];
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break;
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case Microcycle::SelectWord:
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*reinterpret_cast<uint16_t *>(&memory_base[address]) = cycle.value->full;
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break;
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case Microcycle::SelectByte:
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memory_base[address] = cycle.value->halves.low;
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break;
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}
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// Potential writes to ROM and all hardware accesses have already been weeded out.
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cycle.apply(&memory_base[address]);
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return delay;
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}
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@ -582,6 +558,7 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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// The VIA runs at one-tenth of the 68000's clock speed, in sync with the E clock.
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// See: Guide to the Macintosh Hardware Family p149 (PDF p188). Some extra division
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// may occur here in order to provide VSYNC at a proper moment.
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// Possibly route vsync.
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if(time_since_video_update_ < time_until_video_event_) {
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via_clock_ += duration;
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@ -611,8 +588,8 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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// The keyboard also has a clock, albeit a very slow one — 100,000 cycles/second.
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// Its clock and data lines are connected to the VIA.
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keyboard_clock_ += duration;
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const auto keyboard_ticks = keyboard_clock_.divide(HalfCycles(CLOCK_RATE / 100000));
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if(keyboard_ticks > HalfCycles(0)) {
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if(keyboard_clock_ >= KEYBOARD_CLOCK_RATE) {
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const auto keyboard_ticks = keyboard_clock_.divide(KEYBOARD_CLOCK_RATE);
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keyboard_.run_for(keyboard_ticks);
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via_.set_control_line_input(MOS::MOS6522::Port::B, MOS::MOS6522::Line::Two, keyboard_.get_data());
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via_.set_control_line_input(MOS::MOS6522::Port::B, MOS::MOS6522::Line::One, keyboard_.get_clock());
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@ -771,7 +748,7 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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Inputs::QuadratureMouse &mouse_;
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};
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CPU::MC68000::Processor<ConcreteMachine, true> mc68000_;
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CPU::MC68000Mk2::Processor<ConcreteMachine, true, true> mc68000_;
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DriveSpeedAccumulator drive_speed_accumulator_;
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IWMActor iwm_;
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@ -318,9 +318,9 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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// Reads one futher word from the program counter and inserts it into
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// the prefetch queue.
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#define Prefetch() \
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captured_interrupt_level_ = bus_interrupt_level_; \
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prefetch_.high = prefetch_.low; \
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ReadProgramWord(prefetch_.low)
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ReadProgramWord(prefetch_.low) \
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captured_interrupt_level_ = bus_interrupt_level_;
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// Raises the exception with integer vector x — x is the vector identifier,
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// not its address.
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