From 821b5358ea85850033e239e84ade71612a088e0a Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Fri, 22 Apr 2022 14:24:12 -0400
Subject: [PATCH] Add TRAP suffix, disambiguate RTR and RTE.

---
 Processors/68000/Implementation/68000Storage.cpp | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Processors/68000/Implementation/68000Storage.cpp b/Processors/68000/Implementation/68000Storage.cpp
index 9a7f059a0..693b21cca 100644
--- a/Processors/68000/Implementation/68000Storage.cpp
+++ b/Processors/68000/Implementation/68000Storage.cpp
@@ -1049,7 +1049,9 @@ struct ProcessorStorageConstructor {
 							DirectMap(DIVU);
 							DirectMap(DIVS);
 
-							case Operation::RTE_RTR:	opname = "RTE/RTR";	break;
+							case Operation::RTE_RTR:
+								opname = (opcode_ == 0x4e77) ? "RTR" : "RTE";
+							break;
 
 							DirectMap(TRAP);
 							DirectMap(TRAPV);
@@ -1133,6 +1135,8 @@ struct ProcessorStorageConstructor {
 								} else {
 									sprintf(tbuf, "%d", val);
 								}
+							} else if(operation_ == Operation::TRAP) {
+								sprintf(tbuf, "%d", opcode_ & 15);
 							} else {
 								const auto val = ((opcode_ >> 9)&7);
 								sprintf(tbuf, "%d", val ? val : 8);
@@ -3307,6 +3311,7 @@ struct ProcessorStorageConstructor {
 						break;
 
 						case Decoder::TRAP: {
+							dumper.set_source(Quick);
 							// TRAP involves some oddly-sequenced stack writes, so is calculated
 							// at runtime; also the same sequence is used for illegal instructions.
 							// So the entirety is scheduled at runtime.