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https://github.com/TomHarte/CLK.git
synced 2024-11-26 08:49:37 +00:00
Cuts a third from the Program
struct.
Observation: [source/destination]_address are always one of the address registers. So you can fit both within a single byte. Net effect: around a 12% reduction in execution costs, given that this reduces the size of the instructions table from 3mb to 2mb.
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@ -365,9 +365,9 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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case int(MicroOp::Action::None): break;
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#define source() active_program_->source
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#define source_address() active_program_->source_address
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#define source_address() address_[active_program_->source_dest >> 4]
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#define destination() active_program_->destination
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#define destination_address() active_program_->destination_address
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#define destination_address() address_[active_program_->source_dest & 0x0f]
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case int(MicroOp::Action::PerformOperation):
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#define sub_overflow() ((result ^ destination) & (destination ^ source))
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@ -1157,7 +1157,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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const auto mode = (decoded_instruction_.full >> 3) & 7; \
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uint32_t start_address; \
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if(mode <= 4) { \
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start_address = destination_address()->full; \
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start_address = destination_address().full; \
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} else { \
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start_address = effective_address_[1].full; \
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} \
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@ -1996,11 +1996,11 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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#define op_add(x, y) x += y
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#define op_sub(x, y) x -= y
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#define Adjust(op, quantity, effect) \
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case int(op) | MicroOp::SourceMask: effect(source_address()->full, quantity); break; \
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case int(op) | MicroOp::DestinationMask: effect(destination_address()->full, quantity); break; \
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case int(op) | MicroOp::SourceMask: effect(source_address().full, quantity); break; \
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case int(op) | MicroOp::DestinationMask: effect(destination_address().full, quantity); break; \
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case int(op) | MicroOp::SourceMask | MicroOp::DestinationMask: \
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effect(destination_address()->full, quantity); \
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effect(source_address()->full, quantity); \
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effect(destination_address().full, quantity); \
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effect(source_address().full, quantity); \
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break;
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Adjust(MicroOp::Action::Decrement1, 1, op_sub);
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@ -2056,16 +2056,16 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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break;
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case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask:
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effective_address_[0] = u_extend16(prefetch_queue_.halves.low.full) + source_address()->full;
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effective_address_[0] = u_extend16(prefetch_queue_.halves.low.full) + source_address().full;
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break;
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case int(MicroOp::Action::CalcD16An) | MicroOp::DestinationMask:
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effective_address_[1] = u_extend16(prefetch_queue_.halves.low.full) + destination_address()->full;
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effective_address_[1] = u_extend16(prefetch_queue_.halves.low.full) + destination_address().full;
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break;
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case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask | MicroOp::DestinationMask:
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effective_address_[0] = u_extend16(prefetch_queue_.halves.high.full) + source_address()->full;
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effective_address_[1] = u_extend16(prefetch_queue_.halves.low.full) + destination_address()->full;
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effective_address_[0] = u_extend16(prefetch_queue_.halves.high.full) + source_address().full;
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effective_address_[1] = u_extend16(prefetch_queue_.halves.low.full) + destination_address().full;
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break;
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#define CalculateD8AnXn(data, source, target) {\
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@ -2080,16 +2080,16 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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} \
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}
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case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask: {
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CalculateD8AnXn(prefetch_queue_.halves.low, source_address()->full, effective_address_[0]);
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CalculateD8AnXn(prefetch_queue_.halves.low, source_address().full, effective_address_[0]);
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} break;
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case int(MicroOp::Action::CalcD8AnXn) | MicroOp::DestinationMask: {
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CalculateD8AnXn(prefetch_queue_.halves.low, destination_address()->full, effective_address_[1]);
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CalculateD8AnXn(prefetch_queue_.halves.low, destination_address().full, effective_address_[1]);
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} break;
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case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask | MicroOp::DestinationMask: {
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CalculateD8AnXn(prefetch_queue_.halves.high, source_address()->full, effective_address_[0]);
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CalculateD8AnXn(prefetch_queue_.halves.low, destination_address()->full, effective_address_[1]);
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CalculateD8AnXn(prefetch_queue_.halves.high, source_address().full, effective_address_[0]);
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CalculateD8AnXn(prefetch_queue_.halves.low, destination_address().full, effective_address_[1]);
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} break;
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case int(MicroOp::Action::CalcD8PCXn) | MicroOp::SourceMask: {
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@ -2140,16 +2140,16 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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break;
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case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::SourceMask:
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effective_address_[0] = *active_program_->source_address;
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effective_address_[0] = source_address();
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break;
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case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::DestinationMask:
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effective_address_[1] = *active_program_->destination_address;
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effective_address_[1] = destination_address();
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break;
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case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::SourceMask | MicroOp::DestinationMask:
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effective_address_[0] = *active_program_->source_address;
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effective_address_[1] = *active_program_->destination_address;
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effective_address_[0] = source_address();
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effective_address_[1] = destination_address();
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break;
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}
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@ -862,10 +862,6 @@ struct ProcessorStorageConstructor {
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// Temporary storage for the Program fields.
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ProcessorBase::Program program;
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// if(instruction == 0x4879) {
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// printf("");
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// }
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#define dec(n) decrement_action(is_long_word_access, is_byte_access, n)
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#define inc(n) increment_action(is_long_word_access, is_byte_access, n)
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@ -2478,7 +2474,7 @@ struct ProcessorStorageConstructor {
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program.set_destination(storage_, An, data_register);
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const int mode = combined_mode(ea_mode, ea_register);
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program.source_address = &storage_.address_[ea_register];
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program.set_source_address(storage_, ea_register);
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program.source =
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(mode == Ind) ?
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&storage_.address_[ea_register] :
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@ -344,29 +344,44 @@ class ProcessorStorage {
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non-pointer fields doesn't seem to be helpful immediately.)
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*/
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struct Program {
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Operation operation;
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uint8_t source_dest = 0;
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bool requires_supervisor = false;
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MicroOp *micro_operations = nullptr;
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RegisterPair32 *source = nullptr;
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RegisterPair32 *destination = nullptr;
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RegisterPair32 *source_address = nullptr;
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RegisterPair32 *destination_address = nullptr;
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Operation operation;
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bool requires_supervisor = false;
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void set_source_address(ProcessorStorage &storage, int index) {
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source_dest = uint8_t((source_dest & 0x0f) | (index << 4));
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}
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void set_destination_address(ProcessorStorage &storage, int index) {
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source_dest = uint8_t((source_dest & 0xf0) | index);
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}
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void set_source(ProcessorStorage &storage, RegisterPair32 *target) {
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source = target;
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}
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void set_destination(ProcessorStorage &storage, RegisterPair32 *target) {
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destination = target;
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}
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void set_source(ProcessorStorage &storage, int mode, int reg) {
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source_address = &storage.address_[reg];
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set_source_address(storage, reg);
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switch(mode) {
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case 0: source = &storage.data_[reg]; break;
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case 1: source = &storage.address_[reg]; break;
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default: source = &storage.source_bus_data_[0]; break;
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case 0: set_source(storage, &storage.data_[reg]); break;
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case 1: set_source(storage, &storage.address_[reg]); break;
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default: set_source(storage, &storage.source_bus_data_[0]); break;
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}
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}
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void set_destination(ProcessorStorage &storage, int mode, int reg) {
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destination_address = &storage.address_[reg];
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set_destination_address(storage, reg);
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switch(mode) {
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case 0: destination = &storage.data_[reg]; break;
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case 1: destination = &storage.address_[reg]; break;
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default: destination = &storage.destination_bus_data_[0]; break;
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case 0: set_destination(storage, &storage.data_[reg]); break;
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case 1: set_destination(storage, &storage.address_[reg]); break;
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default: set_destination(storage, &storage.destination_bus_data_[0]); break;
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}
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}
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};
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