diff --git a/Processors/6502Esque/6502Esque.hpp b/Processors/6502Esque/6502Esque.hpp
index c4006efbb..c7e2367bc 100644
--- a/Processors/6502Esque/6502Esque.hpp
+++ b/Processors/6502Esque/6502Esque.hpp
@@ -99,17 +99,17 @@ enum class BusOperation {
 /*!
 	For a machine watching only the RWB line, evaluates to @c true if the operation should be treated as a read; @c false otherwise.
 */
-#define isReadOperation(v)		(v <= CPU::MOS6502Esque::BusOperation::InternalOperationRead)
+constexpr bool isReadOperation(BusOperation op) { return op <= BusOperation::InternalOperationRead; }
 
 /*!
 	For a machine watching only the RWB line, evaluates to @c true if the operation is any sort of write; @c false otherwise.
 */
-#define isWriteOperation(v)		(v >= CPU::MOS6502Esque::BusOperation::Write)
+constexpr bool isWriteOperation(BusOperation op) { return op >= BusOperation::Write; }
 
 /*!
 	Evaluates to @c true if the operation actually expects a response; @c false otherwise.
 */
-#define isAccessOperation(v)	((v <= CPU::MOS6502Esque::BusOperation::ReadVector) || (v == CPU::MOS6502Esque::BusOperation::Write))
+constexpr bool isAccessOperation(BusOperation op) { return op <= BusOperation::ReadVector || op == BusOperation::Write; }
 
 /*!
 	A class providing empty implementations of the methods a 6502 uses to access the bus. To wire the 6502 to a bus,
@@ -136,7 +136,11 @@ template <typename addr_t> class BusHandler {
 			during some periods; one way to simulate that is to have the bus handler return a number other than
 			Cycles(1) to describe lengthened bus cycles.
 		*/
-		Cycles perform_bus_operation([[maybe_unused]] BusOperation operation, [[maybe_unused]] addr_t address, [[maybe_unused]] uint8_t *value) {
+		Cycles perform_bus_operation(
+			[[maybe_unused]] BusOperation operation,
+			[[maybe_unused]] addr_t address,
+			[[maybe_unused]] uint8_t *value
+		) {
 			return Cycles(1);
 		}
 };