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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 08:49:37 +00:00

Corrected timestamp reporting by the all-RAM Z80.

This commit is contained in:
Thomas Harte 2017-07-26 19:47:39 -04:00
parent 81a3899381
commit 847e49ccdf
3 changed files with 7 additions and 1 deletions

View File

@ -18,7 +18,7 @@ namespace CPU {
class AllRAMProcessor { class AllRAMProcessor {
public: public:
AllRAMProcessor(size_t memory_size); AllRAMProcessor(size_t memory_size);
uint32_t get_timestamp(); virtual uint32_t get_timestamp();
void set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data); void set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data);
void get_data_at_address(uint16_t startAddress, size_t length, uint8_t *data); void get_data_at_address(uint16_t startAddress, size_t length, uint8_t *data);

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@ -94,6 +94,10 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
void set_wait_line(bool value) { void set_wait_line(bool value) {
CPU::Z80::Processor<ConcreteAllRAMProcessor>::set_wait_line(value); CPU::Z80::Processor<ConcreteAllRAMProcessor>::set_wait_line(value);
} }
uint32_t get_timestamp() {
return timestamp_ >> 1;
}
}; };
} }

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@ -38,6 +38,8 @@ class AllRAMProcessor:
virtual void set_non_maskable_interrupt_line(bool value) = 0; virtual void set_non_maskable_interrupt_line(bool value) = 0;
virtual void set_wait_line(bool value) = 0; virtual void set_wait_line(bool value) = 0;
virtual uint32_t get_timestamp() = 0;
protected: protected:
MemoryAccessDelegate *delegate_; MemoryAccessDelegate *delegate_;
AllRAMProcessor() : ::CPU::AllRAMProcessor(65536), delegate_(nullptr) {} AllRAMProcessor() : ::CPU::AllRAMProcessor(65536), delegate_(nullptr) {}