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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 08:49:37 +00:00

Revised guess; there's a jump to C02E almost immediately.

This commit is contained in:
Thomas Harte 2021-06-14 21:40:19 -04:00
parent fe04410681
commit 853914480c

View File

@ -28,17 +28,21 @@ class ConcreteMachine:
// Request a clock of 4Mhz; this'll be mapped upwards for Nick and Dave elsewhere. // Request a clock of 4Mhz; this'll be mapped upwards for Nick and Dave elsewhere.
set_clock_rate(4'000'000); set_clock_rate(4'000'000);
const auto request = ROM::Request(ROM::Name::EnterpriseEXOS); constexpr ROM::Name exos_name = ROM::Name::EnterpriseEXOS;
const auto request = ROM::Request(exos_name);
auto roms = rom_fetcher(request); auto roms = rom_fetcher(request);
if(!request.validate(roms)) { if(!request.validate(roms)) {
throw ROMMachine::Error::MissingROMs; throw ROMMachine::Error::MissingROMs;
} }
const auto &exos = roms.find(exos_name)->second;
memcpy(exos_.data(), exos.data(), std::min(exos_.size(), exos.size()));
// Take a reasonable guess at the initial memory configuration. // Take a reasonable guess at the initial memory configuration.
page<0>(0x00); page<0>(0x00);
page<1>(0x01); page<1>(0x00);
page<2>(0xfe); page<2>(0x00);
page<3>(0xff); page<3>(0x00);
} }
// MARK: - Z80::BusHandler. // MARK: - Z80::BusHandler.
@ -52,7 +56,12 @@ class ConcreteMachine:
default: break; default: break;
case CPU::Z80::PartialMachineCycle::Input: case CPU::Z80::PartialMachineCycle::Input:
printf("Unhandled input: %04x\n", address);
assert(false);
break;
case CPU::Z80::PartialMachineCycle::Output: case CPU::Z80::PartialMachineCycle::Output:
printf("Unhandled output: %04x\n", address);
assert(false); assert(false);
break; break;