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Eliminate various other errant spaces.

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This commit is contained in:
Thomas Harte
2023-05-16 16:40:09 -04:00
parent f821b60430
commit 8578dfbf22
55 changed files with 86 additions and 86 deletions
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Processors/6502/Implementation/6502Implementation.hpp
+1 -1
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@@ -172,7 +172,7 @@ template <Personality personality, typename T, bool uses_ready_line> void Proces
case CyclePullOperand: s_++; read_mem(operand_, s_ | 0x100); break;
case OperationSetFlagsFromOperand: set_flags(operand_); continue;
case OperationSetOperandFromFlagsWithBRKSet: operand_ = flags_.get(); continue;
case OperationSetOperandFromFlags: operand_ = flags_.get() & ~Flag::Break; continue;
case OperationSetOperandFromFlags: operand_ = flags_.get() & ~Flag::Break; continue;
case OperationSetFlagsFromA: flags_.set_nz(a_); continue;
case OperationSetFlagsFromX: flags_.set_nz(x_); continue;
case OperationSetFlagsFromY: flags_.set_nz(y_); continue;
Processors/68000/Implementation/68000Implementation.hpp
+2 -2
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@@ -410,7 +410,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// Perform the RESET exception, which seeds the stack pointer and program
// counter, populates the prefetch queue, and then moves to instruction dispatch.
BeginState(Reset):
IdleBus(7); // (n-)*5 nn
IdleBus(7); // (n-)*5 nn
// Establish general reset state.
status_.begin_exception(7);
@@ -493,7 +493,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
//
// And the documented bus pattern is:
//
// nn ns ns nS ns ns ns nS nV nv np n np
// nn ns ns nS ns ns ns nS nV nv np n np
//
// So, based on the hoopy ordering of a standard exception, maybe:
//
Processors/Z80/Implementation/PartialMachineCycle.cpp
+1 -1
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@@ -18,7 +18,7 @@ PartialMachineCycle::PartialMachineCycle(const PartialMachineCycle &rhs) noexcep
was_requested(rhs.was_requested) {}
PartialMachineCycle::PartialMachineCycle(Operation operation, HalfCycles length, uint16_t *address, uint8_t *value, bool was_requested) noexcept :
operation(operation), length(length), address(address), value(value), was_requested(was_requested) {}
operation(operation), length(length), address(address), value(value), was_requested(was_requested) {}
PartialMachineCycle::PartialMachineCycle() noexcept :
operation(Internal), length(0), address(nullptr), value(nullptr), was_requested(false) {}
Processors/Z80/Implementation/Z80Implementation.hpp
+1 -1
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@@ -523,7 +523,7 @@ template < class T,
uint8_t result = a_ - temp8_; \
const uint8_t halfResult = (a_&0xf) - (temp8_&0xf); \
\
parity_overflow_result_ = bc_.full ? Flag::Parity : 0; \
parity_overflow_result_ = bc_.full ? Flag::Parity : 0; \
half_carry_result_ = halfResult; \
subtract_flag_ = Flag::Subtract; \
sign_result_ = zero_result_ = result; \
Processors/Z80/Implementation/Z80Storage.cpp
+6 -6
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@@ -394,22 +394,22 @@ void ProcessorStorage::assemble_base_page(InstructionPage &target, RegisterPair1
/* 0x3f CCF */ Sequence({MicroOp::CCF}),
/* 0x40 LD B, B; 0x41 LD B, C; 0x42 LD B, D; 0x43 LD B, E; 0x44 LD B, H; 0x45 LD B, L; 0x46 LD B, (HL); 0x47 LD B, A */
/* 0x40 LD B, B; 0x41 LD B, C; 0x42 LD B, D; 0x43 LD B, E; 0x44 LD B, H; 0x45 LD B, L; 0x46 LD B, (HL); 0x47 LD B, A */
LD_GROUP(bc_.halves.high, bc_.halves.high),
/* 0x48 LD C, B; 0x49 LD C, C; 0x4a LD C, D; 0x4b LD C, E; 0x4c LD C, H; 0x4d LD C, L; 0x4e LD C, (HL); 0x4f LD C, A */
/* 0x48 LD C, B; 0x49 LD C, C; 0x4a LD C, D; 0x4b LD C, E; 0x4c LD C, H; 0x4d LD C, L; 0x4e LD C, (HL); 0x4f LD C, A */
LD_GROUP(bc_.halves.low, bc_.halves.low),
/* 0x50 LD D, B; 0x51 LD D, C; 0x52 LD D, D; 0x53 LD D, E; 0x54 LD D, H; 0x55 LD D, L; 0x56 LD D, (HL); 0x57 LD D, A */
/* 0x50 LD D, B; 0x51 LD D, C; 0x52 LD D, D; 0x53 LD D, E; 0x54 LD D, H; 0x55 LD D, L; 0x56 LD D, (HL); 0x57 LD D, A */
LD_GROUP(de_.halves.high, de_.halves.high),
/* 0x58 LD E, B; 0x59 LD E, C; 0x5a LD E, D; 0x5b LD E, E; 0x5c LD E, H; 0x5d LD E, L; 0x5e LD E, (HL); 0x5f LD E, A */
/* 0x58 LD E, B; 0x59 LD E, C; 0x5a LD E, D; 0x5b LD E, E; 0x5c LD E, H; 0x5d LD E, L; 0x5e LD E, (HL); 0x5f LD E, A */
LD_GROUP(de_.halves.low, de_.halves.low),
/* 0x60 LD H, B; 0x61 LD H, C; 0x62 LD H, D; 0x63 LD H, E; 0x64 LD H, H; 0x65 LD H, L; 0x66 LD H, (HL); 0x67 LD H, A */
/* 0x60 LD H, B; 0x61 LD H, C; 0x62 LD H, D; 0x63 LD H, E; 0x64 LD H, H; 0x65 LD H, L; 0x66 LD H, (HL); 0x67 LD H, A */
LD_GROUP(index.halves.high, hl_.halves.high),
/* 0x68 LD L, B; 0x69 LD L, C; 0x6a LD L, D; 0x6b LD L, E; 0x6c LD L, H; 0x6d LD H, L; 0x6e LD L, (HL); 0x6f LD L, A */
/* 0x68 LD L, B; 0x69 LD L, C; 0x6a LD L, D; 0x6b LD L, E; 0x6c LD L, H; 0x6d LD H, L; 0x6e LD L, (HL); 0x6f LD L, A */
LD_GROUP(index.halves.low, hl_.halves.low),
/* 0x70 LD (HL), B */ Sequence(INDEX(), Write(INDEX_ADDR(), bc_.halves.high)),