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Improve documentation, pin down read/write times.
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@@ -206,7 +206,11 @@ template<Model model> class ConcreteMachine:
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// the read/write, then complete the bus cycle. Only via the 48/128k Spectrum contended
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// timings am I now learning what happens with MREQ during extended read/write bus cycles
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// (i.e. those longer than 3 cycles)
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advance(cycle.length);
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if(cycle.length > HalfCycles(5)) {
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advance(HalfCycles(5));
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} else {
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advance(cycle.length);
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}
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switch(cycle.operation) {
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default: break;
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@@ -364,6 +368,9 @@ template<Model model> class ConcreteMachine:
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break;
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}
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if(cycle.length > HalfCycles(5)) {
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advance(cycle.length - HalfCycles(5));
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}
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return HalfCycles(0);
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}
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