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Improve documentation, pin down read/write times.

This commit is contained in:
Thomas Harte
2021-04-01 12:38:58 -04:00
parent 687c05365e
commit 87317f5673
2 changed files with 16 additions and 3 deletions
+8 -1
View File
@@ -206,7 +206,11 @@ template<Model model> class ConcreteMachine:
// the read/write, then complete the bus cycle. Only via the 48/128k Spectrum contended
// timings am I now learning what happens with MREQ during extended read/write bus cycles
// (i.e. those longer than 3 cycles)
advance(cycle.length);
if(cycle.length > HalfCycles(5)) {
advance(HalfCycles(5));
} else {
advance(cycle.length);
}
switch(cycle.operation) {
default: break;
@@ -364,6 +368,9 @@ template<Model model> class ConcreteMachine:
break;
}
if(cycle.length > HalfCycles(5)) {
advance(cycle.length - HalfCycles(5));
}
return HalfCycles(0);
}