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mirror of https://github.com/TomHarte/CLK.git synced 2024-06-29 00:29:34 +00:00

Adds enough raster position to return something.

This commit is contained in:
Thomas Harte 2021-07-22 21:45:51 -04:00
parent 2bc9af09e1
commit 87d2fc1491
3 changed files with 30 additions and 2 deletions

View File

@ -74,6 +74,8 @@ class ConcreteMachine:
cia_a_.run_for(cycle.length);
cia_b_.run_for(cycle.length);
chipset_.run_for(cycle.length);
// Check for assertion of reset.
if(cycle.operation & Microcycle::Reset) {
memory_.reset();

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@ -20,11 +20,20 @@ Chipset::Chipset(uint16_t *ram, size_t size) :
blitter_(ram, size) {
}
void Chipset::run_for(HalfCycles length) {
// Update raster position.
// TODO: actual graphics, why not?
x_ += length.as<int>();
y_ = (y_ + x_ / (227 + (y_&1))) % 262;
x_ %= 227;
}
void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
using Microcycle = CPU::MC68000::Microcycle;
#define RW(address) (address & 0xffe) | ((cycle.operation & Microcycle::Read) << 7)
#define Read(address) address | 0x1000
#define RW(address) (address & 0xffe) | ((cycle.operation & Microcycle::Read) << 12)
#define Read(address) address | (Microcycle::Read << 12)
#define Write(address) address
#define ApplySetClear(target) { \
@ -42,6 +51,18 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
assert(false);
break;
// Position polling.
case Read(0x004): {
const uint16_t position = uint16_t(y_ >> 8);
LOG("Read vertical position high " << PADHEX(4) << position);
cycle.set_value16(position);
} break;
case Read(0x006): {
const uint16_t position = uint16_t((x_ << 8) | (y_ & 0xff));
LOG("Read vertical position low " << PADHEX(4) << position);
cycle.set_value16(position);
} break;
// Disk DMA.
case Write(0x020): case Write(0x022): case Write(0x024):
case Write(0x026):

View File

@ -55,6 +55,11 @@ class Chipset {
void set_stop_and_control(uint16_t value);
void set_image_data(int slot, uint16_t value);
} sprites_[8];
// MARK: - Raster.
int x_ = 0, y_ = 0;
int line_length_ = 227;
};
}