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https://github.com/TomHarte/CLK.git
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Adds enough raster position to return something.
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2bc9af09e1
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@ -74,6 +74,8 @@ class ConcreteMachine:
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cia_a_.run_for(cycle.length);
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cia_b_.run_for(cycle.length);
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chipset_.run_for(cycle.length);
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// Check for assertion of reset.
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if(cycle.operation & Microcycle::Reset) {
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memory_.reset();
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@ -20,11 +20,20 @@ Chipset::Chipset(uint16_t *ram, size_t size) :
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blitter_(ram, size) {
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}
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void Chipset::run_for(HalfCycles length) {
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// Update raster position.
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// TODO: actual graphics, why not?
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x_ += length.as<int>();
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y_ = (y_ + x_ / (227 + (y_&1))) % 262;
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x_ %= 227;
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}
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void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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using Microcycle = CPU::MC68000::Microcycle;
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#define RW(address) (address & 0xffe) | ((cycle.operation & Microcycle::Read) << 7)
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#define Read(address) address | 0x1000
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#define RW(address) (address & 0xffe) | ((cycle.operation & Microcycle::Read) << 12)
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#define Read(address) address | (Microcycle::Read << 12)
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#define Write(address) address
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#define ApplySetClear(target) { \
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@ -42,6 +51,18 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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assert(false);
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break;
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// Position polling.
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case Read(0x004): {
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const uint16_t position = uint16_t(y_ >> 8);
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LOG("Read vertical position high " << PADHEX(4) << position);
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cycle.set_value16(position);
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} break;
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case Read(0x006): {
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const uint16_t position = uint16_t((x_ << 8) | (y_ & 0xff));
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LOG("Read vertical position low " << PADHEX(4) << position);
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cycle.set_value16(position);
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} break;
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// Disk DMA.
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case Write(0x020): case Write(0x022): case Write(0x024):
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case Write(0x026):
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@ -55,6 +55,11 @@ class Chipset {
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void set_stop_and_control(uint16_t value);
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void set_image_data(int slot, uint16_t value);
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} sprites_[8];
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// MARK: - Raster.
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int x_ = 0, y_ = 0;
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int line_length_ = 227;
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};
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}
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