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https://github.com/TomHarte/CLK.git
synced 2024-11-22 12:33:29 +00:00
Mildly reduce cost of 8-byte ROM overlay.
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2a0375e9c2
commit
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@ -100,8 +100,7 @@ class ConcreteMachine:
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Memory::PackBigEndian16(roms.find(rom_name)->second, rom_);
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// Set up basic memory map.
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memory_map_[0] = BusDevice::MostlyRAM;
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int c = 1;
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int c = 0;
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for(; c < int(ram_.size() >> 16); ++c) memory_map_[c] = BusDevice::RAM;
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for(; c < 0x40; ++c) memory_map_[c] = BusDevice::Floating;
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for(; c < 0xff; ++c) memory_map_[c] = BusDevice::Unassigned;
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@ -118,6 +117,9 @@ class ConcreteMachine:
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memory_map_[0xfa] = memory_map_[0xfb] = BusDevice::Cartridge;
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memory_map_[0xff] = BusDevice::IO;
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// Copy the first 8 bytes of ROM into RAM.
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reinstall_rom_vector();
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midi_acia_->set_interrupt_delegate(this);
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keyboard_acia_->set_interrupt_delegate(this);
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@ -249,18 +251,15 @@ class ConcreteMachine:
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uint8_t *memory = nullptr;
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switch(memory_map_[address >> 16]) {
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default:
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case BusDevice::MostlyRAM:
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if(address < 8) {
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memory = rom_.data();
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break;
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}
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[[fallthrough]];
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case BusDevice::RAM:
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memory = ram_.data();
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break;
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case BusDevice::ROM:
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memory = rom_.data();
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if(!(operation & Microcycle::Read)) {
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return delay;
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}
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address -= rom_start_;
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break;
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@ -408,6 +407,9 @@ class ConcreteMachine:
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}
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// If control has fallen through to here, the access is either a read from ROM, or a read or write to RAM.
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//
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// In both write cases, immediately reinstall the first eight bytes of RAM from ROM, so that any write to
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// that area is in effect a no-op. This is cheaper than the conditionality of actually checking.
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switch(operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
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default:
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break;
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@ -422,17 +424,23 @@ class ConcreteMachine:
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if(address >= video_range_.low_address && address < video_range_.high_address)
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video_.flush();
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*reinterpret_cast<uint16_t *>(&memory[address]) = cycle.value->w;
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reinstall_rom_vector();
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break;
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case Microcycle::SelectByte:
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if(address >= video_range_.low_address && address < video_range_.high_address)
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video_.flush();
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memory[address] = cycle.value->b;
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reinstall_rom_vector();
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break;
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}
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return HalfCycles(0);
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}
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void reinstall_rom_vector() {
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std::copy(rom_.begin(), rom_.begin() + 8, ram_.begin());
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}
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void flush_output(int outputs) final {
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dma_.flush();
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mfp_.flush();
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@ -520,8 +528,6 @@ class ConcreteMachine:
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uint32_t rom_start_ = 0;
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enum class BusDevice {
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/// A mostly RAM page is one that returns ROM for the first 8 bytes, RAM elsewhere.
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MostlyRAM,
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/// Allows reads and writes to ram_.
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RAM,
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/// Nothing is mapped to this area, and it also doesn't trigger an exception upon access.
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