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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-21 21:33:54 +00:00

Fix base address, delays.

This commit is contained in:
Thomas Harte 2024-09-06 20:55:26 -04:00
parent 5ca1659bcc
commit 88248d7062
2 changed files with 7 additions and 7 deletions

View File

@ -310,7 +310,7 @@ uint8_t VideoOutput::run_for(const Cycles cycles) {
output_ = stage;
if(stage == OutputStage::Pixels) {
initial_output_target_ = current_output_target_ = crt_.begin_data(mode_40 ? 320 : 640);
initial_output_target_ = current_output_target_ = crt_.begin_data(640);//crt_.begin_data(mode_40 ? 320 : 640);
}
}
++output_length_;
@ -352,15 +352,15 @@ uint8_t VideoOutput::run_for(const Cycles cycles) {
void VideoOutput::write(int address, uint8_t value) {
switch(address & 0xf) {
case 0x02:
screen_base =
(screen_base & 0b0111'1110'0000'0000) |
((value << 1) & 0b0000'0001'1100'0000);
break;
case 0x03:
screen_base =
(screen_base & 0b0111'1110'0000'0000) |
((value << 1) & 0b0000'0001'1100'0000);
break;
case 0x03:
screen_base =
((value << 9) & 0b0111'1110'0000'0000) |
(screen_base & 0b0000'0001'1100'0000);
break;
case 0x07: {
uint8_t mode = (value >> 3)&7;
mode_40 = mode >= 4;

View File

@ -59,7 +59,7 @@ class VideoOutput {
/// RAM access that is first signalled in the upcoming cycle.
Cycles ram_delay() {
if(!mode_40 && !in_blank()) {
return 2 + h_active - h_count;
return 2 + ((h_active - h_count) >> 3);
}
return io_delay();
}