From de218611e445d520002bbb807a722b051f1aa5aa Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Fri, 1 Sep 2017 20:49:24 -0400 Subject: [PATCH 1/3] Corrects possible confusion as documentation recommends Cycles(0) as default, but then gives Cycles(1). --- Processors/6502/6502.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Processors/6502/6502.hpp b/Processors/6502/6502.hpp index 7d8e0ea01..fed338612 100644 --- a/Processors/6502/6502.hpp +++ b/Processors/6502/6502.hpp @@ -93,7 +93,7 @@ class BusHandler { Cycles(1) to describe lengthened bus cycles. */ Cycles perform_bus_operation(CPU::MOS6502::BusOperation operation, uint16_t address, uint8_t *value) { - return Cycles(0); + return Cycles(1); } /*! From b034d4e6f8cefa3743b1a53a4fa2d6925c3fc492 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Fri, 1 Sep 2017 20:50:24 -0400 Subject: [PATCH 2/3] Refactors the Z80 to separate out interface and implementation. Following the pattern just established by the 6502, puts all implementation specifics beyond the visibility of a human reading Z80.hpp and in subfolders so as to promote the idea that they shouldn't go out of their way. --- .../Clock Signal.xcodeproj/project.pbxproj | 42 +- Processors/Z80/{ => AllRAM}/Z80AllRAM.cpp | 0 Processors/Z80/{ => AllRAM}/Z80AllRAM.hpp | 4 +- Processors/Z80/Implementation/Z80Base.cpp | 223 ++ .../Z80/Implementation/Z80Implementation.hpp | 1020 +++++++++ Processors/Z80/Implementation/Z80Storage.hpp | 657 ++++++ Processors/Z80/Z80.cpp | 9 - Processors/Z80/Z80.hpp | 2000 ++--------------- 8 files changed, 2060 insertions(+), 1895 deletions(-) rename Processors/Z80/{ => AllRAM}/Z80AllRAM.cpp (100%) rename Processors/Z80/{ => AllRAM}/Z80AllRAM.hpp (95%) create mode 100644 Processors/Z80/Implementation/Z80Base.cpp create mode 100644 Processors/Z80/Implementation/Z80Implementation.hpp create mode 100644 Processors/Z80/Implementation/Z80Storage.hpp delete mode 100644 Processors/Z80/Z80.cpp diff --git a/OSBindings/Mac/Clock Signal.xcodeproj/project.pbxproj b/OSBindings/Mac/Clock Signal.xcodeproj/project.pbxproj index b03b62e9e..9b2a2d417 100644 --- a/OSBindings/Mac/Clock Signal.xcodeproj/project.pbxproj +++ b/OSBindings/Mac/Clock Signal.xcodeproj/project.pbxproj @@ -42,6 +42,8 @@ 4B2E2D9D1C3A070400138695 /* Electron.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B2E2D9B1C3A070400138695 /* Electron.cpp */; }; 4B30512D1D989E2200B4FED8 /* Drive.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B30512B1D989E2200B4FED8 /* Drive.cpp */; }; 4B3051301D98ACC600B4FED8 /* Plus3.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B30512E1D98ACC600B4FED8 /* Plus3.cpp */; }; + 4B322E011F5A2990004EB04C /* Z80AllRAM.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B322DFD1F5A2981004EB04C /* Z80AllRAM.cpp */; }; + 4B322E041F5A2E3C004EB04C /* Z80Base.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B322E031F5A2E3C004EB04C /* Z80Base.cpp */; }; 4B37EE821D7345A6006A09A4 /* BinaryDump.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B37EE801D7345A6006A09A4 /* BinaryDump.cpp */; }; 4B38F3441F2EB3E900D9235D /* StaticAnalyser.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B38F3421F2EB3E900D9235D /* StaticAnalyser.cpp */; }; 4B38F3481F2EC11D00D9235D /* AmstradCPC.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B38F3461F2EC11D00D9235D /* AmstradCPC.cpp */; }; @@ -82,7 +84,6 @@ 4B69FB461C4D950F00B5F0AA /* libz.tbd in Frameworks */ = {isa = PBXBuildFile; fileRef = 4B69FB451C4D950F00B5F0AA /* libz.tbd */; }; 4B6A4C991F58F09E00E3F787 /* 6502Base.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B6A4C951F58F09E00E3F787 /* 6502Base.cpp */; }; 4B6C73BD1D387AE500AFCFCA /* DiskController.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B6C73BB1D387AE500AFCFCA /* DiskController.cpp */; }; - 4B77069D1EC904570053B588 /* Z80.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B77069B1EC904570053B588 /* Z80.cpp */; }; 4B7913CC1DFCD80E00175A82 /* Video.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B7913CA1DFCD80E00175A82 /* Video.cpp */; }; 4B79E4441E3AF38600141F11 /* cassette.png in Resources */ = {isa = PBXBuildFile; fileRef = 4B79E4411E3AF38600141F11 /* cassette.png */; }; 4B79E4451E3AF38600141F11 /* floppy35.png in Resources */ = {isa = PBXBuildFile; fileRef = 4B79E4421E3AF38600141F11 /* floppy35.png */; }; @@ -443,7 +444,6 @@ 4BF829631D8F536B001BAE39 /* SSD.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BF829611D8F536B001BAE39 /* SSD.cpp */; }; 4BF829661D8F732B001BAE39 /* Disk.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BF829641D8F732B001BAE39 /* Disk.cpp */; }; 4BFB9FAE1F467D3A00960122 /* HFE.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BFB9FAC1F467D3A00960122 /* HFE.cpp */; }; - 4BFCA1201ECBDC1500AC40C1 /* Z80AllRAM.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BFCA11D1ECBD9BD00AC40C1 /* Z80AllRAM.cpp */; }; 4BFCA1241ECBDCB400AC40C1 /* AllRAMProcessor.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BFCA1211ECBDCAF00AC40C1 /* AllRAMProcessor.cpp */; }; 4BFCA1271ECBE33200AC40C1 /* TestMachineZ80.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4BFCA1261ECBE33200AC40C1 /* TestMachineZ80.mm */; }; 4BFCA1291ECBE7A700AC40C1 /* zexall.com in Resources */ = {isa = PBXBuildFile; fileRef = 4BFCA1281ECBE7A700AC40C1 /* zexall.com */; }; @@ -539,6 +539,11 @@ 4B30512F1D98ACC600B4FED8 /* Plus3.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = Plus3.hpp; path = Electron/Plus3.hpp; sourceTree = ""; }; 4B322DF31F5A26BF004EB04C /* 6502Implementation.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = 6502Implementation.hpp; sourceTree = ""; }; 4B322DF41F5A2714004EB04C /* 6502Storage.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = 6502Storage.hpp; sourceTree = ""; }; + 4B322DFD1F5A2981004EB04C /* Z80AllRAM.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = Z80AllRAM.cpp; sourceTree = ""; }; + 4B322DFE1F5A2981004EB04C /* Z80AllRAM.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = Z80AllRAM.hpp; sourceTree = ""; }; + 4B322E021F5A29D5004EB04C /* Z80Storage.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Z80Storage.hpp; sourceTree = ""; }; + 4B322E031F5A2E3C004EB04C /* Z80Base.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = Z80Base.cpp; sourceTree = ""; }; + 4B322E051F5A30F5004EB04C /* Z80Implementation.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Z80Implementation.hpp; sourceTree = ""; }; 4B37EE801D7345A6006A09A4 /* BinaryDump.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = BinaryDump.cpp; sourceTree = ""; }; 4B37EE811D7345A6006A09A4 /* BinaryDump.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = BinaryDump.hpp; sourceTree = ""; }; 4B38F3421F2EB3E900D9235D /* StaticAnalyser.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = StaticAnalyser.cpp; path = ../../StaticAnalyser/AmstradCPC/StaticAnalyser.cpp; sourceTree = ""; }; @@ -614,7 +619,6 @@ 4B6A4C951F58F09E00E3F787 /* 6502Base.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = 6502Base.cpp; sourceTree = ""; }; 4B6C73BB1D387AE500AFCFCA /* DiskController.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = DiskController.cpp; sourceTree = ""; }; 4B6C73BC1D387AE500AFCFCA /* DiskController.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = DiskController.hpp; sourceTree = ""; }; - 4B77069B1EC904570053B588 /* Z80.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = Z80.cpp; path = Z80/Z80.cpp; sourceTree = ""; }; 4B77069C1EC904570053B588 /* Z80.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = Z80.hpp; path = Z80/Z80.hpp; sourceTree = ""; }; 4B7913CA1DFCD80E00175A82 /* Video.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = Video.cpp; path = Electron/Video.cpp; sourceTree = ""; }; 4B7913CB1DFCD80E00175A82 /* Video.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = Video.hpp; path = Electron/Video.hpp; sourceTree = ""; }; @@ -1075,8 +1079,6 @@ 4BF829681D8F7361001BAE39 /* File.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = File.hpp; path = ../../StaticAnalyser/Acorn/File.hpp; sourceTree = ""; }; 4BFB9FAC1F467D3A00960122 /* HFE.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = HFE.cpp; sourceTree = ""; }; 4BFB9FAD1F467D3A00960122 /* HFE.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = HFE.hpp; sourceTree = ""; }; - 4BFCA11D1ECBD9BD00AC40C1 /* Z80AllRAM.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = Z80AllRAM.cpp; path = Z80/Z80AllRAM.cpp; sourceTree = ""; }; - 4BFCA11E1ECBD9BD00AC40C1 /* Z80AllRAM.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = Z80AllRAM.hpp; path = Z80/Z80AllRAM.hpp; sourceTree = ""; }; 4BFCA1211ECBDCAF00AC40C1 /* AllRAMProcessor.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = AllRAMProcessor.cpp; sourceTree = ""; }; 4BFCA1221ECBDCAF00AC40C1 /* AllRAMProcessor.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = AllRAMProcessor.hpp; sourceTree = ""; }; 4BFCA1251ECBE33200AC40C1 /* TestMachineZ80.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = TestMachineZ80.h; sourceTree = ""; }; @@ -1288,6 +1290,27 @@ name = Electron; sourceTree = ""; }; + 4B322DFC1F5A2981004EB04C /* AllRAM */ = { + isa = PBXGroup; + children = ( + 4B322DFD1F5A2981004EB04C /* Z80AllRAM.cpp */, + 4B322DFE1F5A2981004EB04C /* Z80AllRAM.hpp */, + ); + name = AllRAM; + path = Z80/AllRAM; + sourceTree = ""; + }; + 4B322DFF1F5A2981004EB04C /* Implementation */ = { + isa = PBXGroup; + children = ( + 4B322E031F5A2E3C004EB04C /* Z80Base.cpp */, + 4B322E051F5A30F5004EB04C /* Z80Implementation.hpp */, + 4B322E021F5A29D5004EB04C /* Z80Storage.hpp */, + ); + name = Implementation; + path = Z80/Implementation; + sourceTree = ""; + }; 4B366DFD1B5C165F0026627B /* Outputs */ = { isa = PBXGroup; children = ( @@ -1529,10 +1552,9 @@ 4B77069E1EC9045B0053B588 /* Z80 */ = { isa = PBXGroup; children = ( - 4B77069B1EC904570053B588 /* Z80.cpp */, 4B77069C1EC904570053B588 /* Z80.hpp */, - 4BFCA11D1ECBD9BD00AC40C1 /* Z80AllRAM.cpp */, - 4BFCA11E1ECBD9BD00AC40C1 /* Z80AllRAM.hpp */, + 4B322DFC1F5A2981004EB04C /* AllRAM */, + 4B322DFF1F5A2981004EB04C /* Implementation */, ); name = Z80; sourceTree = ""; @@ -2749,6 +2771,7 @@ 4B0CCC451C62D0B3001CAC5F /* CRT.cpp in Sources */, 4B8378DC1F336631005CA9E4 /* CharacterMapper.cpp in Sources */, 4B8378E51F3378C4005CA9E4 /* CharacterMapper.cpp in Sources */, + 4B322E041F5A2E3C004EB04C /* Z80Base.cpp in Sources */, 4B8378E21F336920005CA9E4 /* CharacterMapper.cpp in Sources */, 4BCF1FA41DADC3DD0039D2E7 /* Oric.cpp in Sources */, 4BEA525E1DF33323007E74F2 /* Tape.cpp in Sources */, @@ -2790,7 +2813,6 @@ 4B5FADBD1DE31D1500AEC565 /* OricMFMDSK.cpp in Sources */, 4B14978B1EE4AC5E00CE2596 /* StaticAnalyser.cpp in Sources */, 4BA0F68E1EEA0E8400E9489E /* ZX8081.cpp in Sources */, - 4B77069D1EC904570053B588 /* Z80.cpp in Sources */, 4BAB62B51D327F7E00DF5BA0 /* G64.cpp in Sources */, 4BD468F71D8DF41D0084958B /* 1770.cpp in Sources */, 4BD3A30B1EE755C800B5B501 /* Video.cpp in Sources */, @@ -2873,7 +2895,6 @@ 4B3BA0CE1D318B44005DD7A7 /* C1540Bridge.mm in Sources */, 4B3BA0D11D318B44005DD7A7 /* TestMachine6502.mm in Sources */, 4B92EACA1B7C112B00246143 /* 6502TimingTests.swift in Sources */, - 4BFCA1201ECBDC1500AC40C1 /* Z80AllRAM.cpp in Sources */, 4BB73EB71B587A5100552FC2 /* AllSuiteATests.swift in Sources */, 4B01A6881F22F0DB001FD6E3 /* Z80MemptrTests.swift in Sources */, 4B121F9B1E06293F00BFDA12 /* PCMSegmentEventSourceTests.mm in Sources */, @@ -2892,6 +2913,7 @@ 4B08A2781EE39306008B7065 /* TestMachine.mm in Sources */, 4BFCA1271ECBE33200AC40C1 /* TestMachineZ80.mm in Sources */, 4B121F951E05E66800BFDA12 /* PCMPatchedTrackTests.mm in Sources */, + 4B322E011F5A2990004EB04C /* Z80AllRAM.cpp in Sources */, ); runOnlyForDeploymentPostprocessing = 0; }; diff --git a/Processors/Z80/Z80AllRAM.cpp b/Processors/Z80/AllRAM/Z80AllRAM.cpp similarity index 100% rename from Processors/Z80/Z80AllRAM.cpp rename to Processors/Z80/AllRAM/Z80AllRAM.cpp diff --git a/Processors/Z80/Z80AllRAM.hpp b/Processors/Z80/AllRAM/Z80AllRAM.hpp similarity index 95% rename from Processors/Z80/Z80AllRAM.hpp rename to Processors/Z80/AllRAM/Z80AllRAM.hpp index 7591ef1d8..ad8da8f0f 100644 --- a/Processors/Z80/Z80AllRAM.hpp +++ b/Processors/Z80/AllRAM/Z80AllRAM.hpp @@ -9,8 +9,8 @@ #ifndef Z80AllRAM_hpp #define Z80AllRAM_hpp -#include "Z80.hpp" -#include "../AllRAMProcessor.hpp" +#include "../Z80.hpp" +#include "../../AllRAMProcessor.hpp" namespace CPU { namespace Z80 { diff --git a/Processors/Z80/Implementation/Z80Base.cpp b/Processors/Z80/Implementation/Z80Base.cpp new file mode 100644 index 000000000..dd78f3f3e --- /dev/null +++ b/Processors/Z80/Implementation/Z80Base.cpp @@ -0,0 +1,223 @@ +// +// Z80Storage.cpp +// Clock Signal +// +// Created by Thomas Harte on 01/09/2017. +// Copyright © 2017 Thomas Harte. All rights reserved. +// + +#include "../Z80.hpp" + +using namespace CPU::Z80; + +ProcessorStorage::ProcessorStorage() : + halt_mask_(0xff), + interrupt_mode_(0), + wait_line_(false), + request_status_(Interrupt::PowerOn), + last_request_status_(Interrupt::PowerOn), + irq_line_(false), + nmi_line_(false), + bus_request_line_(false), + pc_increment_(1), + scheduled_program_counter_(nullptr) { + set_flags(0xff); +} + +void ProcessorStorage::install_default_instruction_set() { + MicroOp conditional_call_untaken_program[] = Sequence(ReadInc(pc_, temp16_.bytes.high)); + copy_program(conditional_call_untaken_program, conditional_call_untaken_program_); + + assemble_base_page(base_page_, hl_, false, cb_page_); + assemble_base_page(dd_page_, ix_, true, ddcb_page_); + assemble_base_page(fd_page_, iy_, true, fdcb_page_); + assemble_ed_page(ed_page_); + + fdcb_page_.r_step = 0; + fd_page_.is_indexed = true; + fdcb_page_.is_indexed = true; + + ddcb_page_.r_step = 0; + dd_page_.is_indexed = true; + ddcb_page_.is_indexed = true; + + assemble_fetch_decode_execute(base_page_, 4); + assemble_fetch_decode_execute(dd_page_, 4); + assemble_fetch_decode_execute(fd_page_, 4); + assemble_fetch_decode_execute(ed_page_, 4); + assemble_fetch_decode_execute(cb_page_, 4); + + assemble_fetch_decode_execute(fdcb_page_, 3); + assemble_fetch_decode_execute(ddcb_page_, 3); + + MicroOp reset_program[] = Sequence(InternalOperation(6), {MicroOp::Reset}); + + // Justification for NMI timing: per Wilf Rigter on the ZX81 (http://www.user.dccnet.com/wrigter/index_files/ZX81WAIT.htm), + // wait cycles occur between T2 and T3 during NMI; extending the refresh cycle is also consistent with my guess + // for the action of other non-four-cycle opcode fetches + MicroOp nmi_program[] = { + { MicroOp::BeginNMI }, + BusOp(ReadOpcodeStart()), + BusOp(ReadOpcodeWait(true)), + BusOp(ReadOpcodeEnd()), + BusOp(Refresh(6)), + Push(pc_), + { MicroOp::JumpTo66, nullptr, nullptr}, + { MicroOp::MoveToNextProgram } + }; + MicroOp irq_mode0_program[] = { + { MicroOp::BeginIRQMode0 }, + BusOp(IntAckStart(5, operation_)), + BusOp(IntWait(operation_)), + BusOp(IntAckEnd(operation_)), + { MicroOp::DecodeOperationNoRChange } + }; + MicroOp irq_mode1_program[] = { + { MicroOp::BeginIRQ }, + BusOp(IntAckStart(7, operation_)), // 7 half cycles (including + + BusOp(IntWait(operation_)), // [potentially 2 half cycles] + + BusOp(IntAckEnd(operation_)), // Implicitly 3 half cycles + + BusOp(Refresh(4)), // 4 half cycles + + Push(pc_), // 12 half cycles = 26 half cycles = 13 cycles + { MicroOp::Move16, &temp16_.full, &pc_.full }, + { MicroOp::MoveToNextProgram } + }; + MicroOp irq_mode2_program[] = { + { MicroOp::BeginIRQ }, + BusOp(IntAckStart(7, temp16_.bytes.low)), + BusOp(IntWait(temp16_.bytes.low)), + BusOp(IntAckEnd(temp16_.bytes.low)), + BusOp(Refresh(4)), + Push(pc_), + { MicroOp::Move8, &ir_.bytes.high, &temp16_.bytes.high }, + Read16(temp16_, pc_), + { MicroOp::MoveToNextProgram } + }; + + copy_program(reset_program, reset_program_); + copy_program(nmi_program, nmi_program_); + copy_program(irq_mode0_program, irq_program_[0]); + copy_program(irq_mode1_program, irq_program_[1]); + copy_program(irq_mode2_program, irq_program_[2]); +} + +void ProcessorBase::reset_power_on() { + request_status_ &= ~Interrupt::PowerOn; + last_request_status_ &= ~Interrupt::PowerOn; +} + +uint16_t ProcessorBase::get_value_of_register(Register r) { + switch (r) { + case Register::ProgramCounter: return pc_.full; + case Register::StackPointer: return sp_.full; + + case Register::A: return a_; + case Register::Flags: return get_flags(); + case Register::AF: return (uint16_t)((a_ << 8) | get_flags()); + case Register::B: return bc_.bytes.high; + case Register::C: return bc_.bytes.low; + case Register::BC: return bc_.full; + case Register::D: return de_.bytes.high; + case Register::E: return de_.bytes.low; + case Register::DE: return de_.full; + case Register::H: return hl_.bytes.high; + case Register::L: return hl_.bytes.low; + case Register::HL: return hl_.full; + + case Register::ADash: return afDash_.bytes.high; + case Register::FlagsDash: return afDash_.bytes.low; + case Register::AFDash: return afDash_.full; + case Register::BDash: return bcDash_.bytes.high; + case Register::CDash: return bcDash_.bytes.low; + case Register::BCDash: return bcDash_.full; + case Register::DDash: return deDash_.bytes.high; + case Register::EDash: return deDash_.bytes.low; + case Register::DEDash: return deDash_.full; + case Register::HDash: return hlDash_.bytes.high; + case Register::LDash: return hlDash_.bytes.low; + case Register::HLDash: return hlDash_.full; + + case Register::IXh: return ix_.bytes.high; + case Register::IXl: return ix_.bytes.low; + case Register::IX: return ix_.full; + case Register::IYh: return iy_.bytes.high; + case Register::IYl: return iy_.bytes.low; + case Register::IY: return iy_.full; + + case Register::R: return ir_.bytes.low; + case Register::I: return ir_.bytes.high; + case Register::Refresh: return ir_.full; + + case Register::IFF1: return iff1_ ? 1 : 0; + case Register::IFF2: return iff2_ ? 1 : 0; + case Register::IM: return (uint16_t)interrupt_mode_; + + case Register::MemPtr: return memptr_.full; + + default: return 0; + } +} + +void ProcessorBase::set_value_of_register(Register r, uint16_t value) { + switch (r) { + case Register::ProgramCounter: pc_.full = value; break; + case Register::StackPointer: sp_.full = value; break; + + case Register::A: a_ = (uint8_t)value; break; + case Register::AF: a_ = (uint8_t)(value >> 8); // deliberate fallthrough... + case Register::Flags: set_flags((uint8_t)value); break; + + case Register::B: bc_.bytes.high = (uint8_t)value; break; + case Register::C: bc_.bytes.low = (uint8_t)value; break; + case Register::BC: bc_.full = value; break; + case Register::D: de_.bytes.high = (uint8_t)value; break; + case Register::E: de_.bytes.low = (uint8_t)value; break; + case Register::DE: de_.full = value; break; + case Register::H: hl_.bytes.high = (uint8_t)value; break; + case Register::L: hl_.bytes.low = (uint8_t)value; break; + case Register::HL: hl_.full = value; break; + + case Register::ADash: afDash_.bytes.high = (uint8_t)value; break; + case Register::FlagsDash: afDash_.bytes.low = (uint8_t)value; break; + case Register::AFDash: afDash_.full = value; break; + case Register::BDash: bcDash_.bytes.high = (uint8_t)value; break; + case Register::CDash: bcDash_.bytes.low = (uint8_t)value; break; + case Register::BCDash: bcDash_.full = value; break; + case Register::DDash: deDash_.bytes.high = (uint8_t)value; break; + case Register::EDash: deDash_.bytes.low = (uint8_t)value; break; + case Register::DEDash: deDash_.full = value; break; + case Register::HDash: hlDash_.bytes.high = (uint8_t)value; break; + case Register::LDash: hlDash_.bytes.low = (uint8_t)value; break; + case Register::HLDash: hlDash_.full = value; break; + + case Register::IXh: ix_.bytes.high = (uint8_t)value; break; + case Register::IXl: ix_.bytes.low = (uint8_t)value; break; + case Register::IX: ix_.full = value; break; + case Register::IYh: iy_.bytes.high = (uint8_t)value; break; + case Register::IYl: iy_.bytes.low = (uint8_t)value; break; + case Register::IY: iy_.full = value; break; + + case Register::R: ir_.bytes.low = (uint8_t)value; break; + case Register::I: ir_.bytes.high = (uint8_t)value; break; + case Register::Refresh: ir_.full = (uint16_t)value; break; + + case Register::IFF1: iff1_ = !!value; break; + case Register::IFF2: iff2_ = !!value; break; + case Register::IM: interrupt_mode_ = value % 3; break; + + case Register::MemPtr: memptr_.full = value; break; + + default: break; + } +} + +PartialMachineCycle::PartialMachineCycle(const PartialMachineCycle &rhs) : + operation(rhs.operation), + length(rhs.length), + address(rhs.address), + value(rhs.value), + was_requested(rhs.was_requested) {} +PartialMachineCycle::PartialMachineCycle(Operation operation, HalfCycles length, uint16_t *address, uint8_t *value, bool was_requested) noexcept : + operation(operation), length(length), address(address), value(value), was_requested(was_requested) {} +PartialMachineCycle::PartialMachineCycle() noexcept : + operation(Internal), length(0), address(nullptr), value(nullptr), was_requested(false) {} diff --git a/Processors/Z80/Implementation/Z80Implementation.hpp b/Processors/Z80/Implementation/Z80Implementation.hpp new file mode 100644 index 000000000..1f449bd0f --- /dev/null +++ b/Processors/Z80/Implementation/Z80Implementation.hpp @@ -0,0 +1,1020 @@ +// +// Z80Implementation.hpp +// Clock Signal +// +// Created by Thomas Harte on 01/09/2017. +// Copyright © 2017 Thomas Harte. All rights reserved. +// + +template < class T, + bool uses_bus_request, + bool uses_wait_line> Processor + ::Processor(T &bus_handler) : + bus_handler_(bus_handler) { + install_default_instruction_set(); +} + +template < class T, + bool uses_bus_request, + bool uses_wait_line> void Processor + ::run_for(const HalfCycles cycles) { +#define advance_operation() \ + pc_increment_ = 1; \ + if(last_request_status_) { \ + halt_mask_ = 0xff; \ + if(last_request_status_ & (Interrupt::PowerOn | Interrupt::Reset)) { \ + request_status_ &= ~Interrupt::PowerOn; \ + scheduled_program_counter_ = reset_program_.data(); \ + } else if(last_request_status_ & Interrupt::NMI) { \ + request_status_ &= ~Interrupt::NMI; \ + scheduled_program_counter_ = nmi_program_.data(); \ + } else if(last_request_status_ & Interrupt::IRQ) { \ + scheduled_program_counter_ = irq_program_[interrupt_mode_].data(); \ + } \ + } else { \ + current_instruction_page_ = &base_page_; \ + scheduled_program_counter_ = base_page_.fetch_decode_execute_data; \ + } + + number_of_cycles_ += cycles; + if(!scheduled_program_counter_) { + advance_operation(); + } + + while(1) { + + do_bus_acknowledge: + while(uses_bus_request && bus_request_line_) { + static PartialMachineCycle bus_acknowledge_cycle = {PartialMachineCycle::BusAcknowledge, HalfCycles(2), nullptr, nullptr, false}; + number_of_cycles_ -= bus_handler_.perform_machine_cycle(bus_acknowledge_cycle) + HalfCycles(1); + if(!number_of_cycles_) { + bus_handler_.flush(); + return; + } + } + + while(true) { + const MicroOp *operation = scheduled_program_counter_; + scheduled_program_counter_++; + +#define set_parity(v) \ + parity_overflow_result_ = (uint8_t)(v^1);\ + parity_overflow_result_ ^= parity_overflow_result_ >> 4;\ + parity_overflow_result_ ^= parity_overflow_result_ << 2;\ + parity_overflow_result_ ^= parity_overflow_result_ >> 1; + + switch(operation->type) { + case MicroOp::BusOperation: + if(number_of_cycles_ < operation->machine_cycle.length) { + scheduled_program_counter_--; + bus_handler_.flush(); + return; + } + if(uses_wait_line && operation->machine_cycle.was_requested) { + if(wait_line_) { + scheduled_program_counter_--; + } else { + continue; + } + } + number_of_cycles_ -= operation->machine_cycle.length; + last_request_status_ = request_status_; + number_of_cycles_ -= bus_handler_.perform_machine_cycle(operation->machine_cycle); + if(uses_bus_request && bus_request_line_) goto do_bus_acknowledge; + break; + case MicroOp::MoveToNextProgram: + advance_operation(); + break; + case MicroOp::DecodeOperation: + refresh_addr_ = ir_; + ir_.bytes.low = (ir_.bytes.low & 0x80) | ((ir_.bytes.low + current_instruction_page_->r_step) & 0x7f); + pc_.full += pc_increment_ & (uint16_t)halt_mask_; + scheduled_program_counter_ = current_instruction_page_->instructions[operation_ & halt_mask_]; + break; + case MicroOp::DecodeOperationNoRChange: + refresh_addr_ = ir_; + pc_.full += pc_increment_ & (uint16_t)halt_mask_; + scheduled_program_counter_ = current_instruction_page_->instructions[operation_ & halt_mask_]; + break; + + case MicroOp::Increment16: (*(uint16_t *)operation->source)++; break; + case MicroOp::IncrementPC: pc_.full += pc_increment_; break; + case MicroOp::Decrement16: (*(uint16_t *)operation->source)--; break; + case MicroOp::Move8: *(uint8_t *)operation->destination = *(uint8_t *)operation->source; break; + case MicroOp::Move16: *(uint16_t *)operation->destination = *(uint16_t *)operation->source; break; + + case MicroOp::AssembleAF: + temp16_.bytes.high = a_; + temp16_.bytes.low = get_flags(); + break; + case MicroOp::DisassembleAF: + a_ = temp16_.bytes.high; + set_flags(temp16_.bytes.low); + break; + +#pragma mark - Logical + +#define set_logical_flags(hf) \ + sign_result_ = zero_result_ = bit53_result_ = a_; \ + set_parity(a_); \ + half_carry_result_ = hf; \ + subtract_flag_ = 0; \ + carry_result_ = 0; + + case MicroOp::And: + a_ &= *(uint8_t *)operation->source; + set_logical_flags(Flag::HalfCarry); + break; + + case MicroOp::Or: + a_ |= *(uint8_t *)operation->source; + set_logical_flags(0); + break; + + case MicroOp::Xor: + a_ ^= *(uint8_t *)operation->source; + set_logical_flags(0); + break; + +#undef set_logical_flags + + case MicroOp::CPL: + a_ ^= 0xff; + subtract_flag_ = Flag::Subtract; + half_carry_result_ = Flag::HalfCarry; + bit53_result_ = a_; + break; + + case MicroOp::CCF: + half_carry_result_ = (uint8_t)(carry_result_ << 4); + carry_result_ ^= Flag::Carry; + subtract_flag_ = 0; + bit53_result_ = a_; + break; + + case MicroOp::SCF: + carry_result_ = Flag::Carry; + half_carry_result_ = 0; + subtract_flag_ = 0; + bit53_result_ = a_; + break; + +#pragma mark - Flow control + + case MicroOp::DJNZ: + bc_.bytes.high--; + if(!bc_.bytes.high) { + advance_operation(); + } + break; + + case MicroOp::CalculateRSTDestination: + memptr_.full = operation_ & 0x38; + break; + +#pragma mark - 8-bit arithmetic + +#define set_arithmetic_flags(sub, b53) \ + sign_result_ = zero_result_ = (uint8_t)result; \ + carry_result_ = (uint8_t)(result >> 8); \ + half_carry_result_ = (uint8_t)half_result; \ + parity_overflow_result_ = (uint8_t)(overflow >> 5); \ + subtract_flag_ = sub; \ + bit53_result_ = (uint8_t)b53; + + case MicroOp::CP8: { + uint8_t value = *(uint8_t *)operation->source; + int result = a_ - value; + int half_result = (a_&0xf) - (value&0xf); + + // overflow for a subtraction is when the signs were originally + // different and the result is different again + int overflow = (value^a_) & (result^a_); + + // the 5 and 3 flags come from the operand, atypically + set_arithmetic_flags(Flag::Subtract, value); + } break; + + case MicroOp::SUB8: { + uint8_t value = *(uint8_t *)operation->source; + int result = a_ - value; + int half_result = (a_&0xf) - (value&0xf); + + // overflow for a subtraction is when the signs were originally + // different and the result is different again + int overflow = (value^a_) & (result^a_); + + a_ = (uint8_t)result; + set_arithmetic_flags(Flag::Subtract, result); + } break; + + case MicroOp::SBC8: { + uint8_t value = *(uint8_t *)operation->source; + int result = a_ - value - (carry_result_ & Flag::Carry); + int half_result = (a_&0xf) - (value&0xf) - (carry_result_ & Flag::Carry); + + // overflow for a subtraction is when the signs were originally + // different and the result is different again + int overflow = (value^a_) & (result^a_); + + a_ = (uint8_t)result; + set_arithmetic_flags(Flag::Subtract, result); + } break; + + case MicroOp::ADD8: { + uint8_t value = *(uint8_t *)operation->source; + int result = a_ + value; + int half_result = (a_&0xf) + (value&0xf); + + // overflow for addition is when the signs were originally + // the same and the result is different + int overflow = ~(value^a_) & (result^a_); + + a_ = (uint8_t)result; + set_arithmetic_flags(0, result); + } break; + + case MicroOp::ADC8: { + uint8_t value = *(uint8_t *)operation->source; + int result = a_ + value + (carry_result_ & Flag::Carry); + int half_result = (a_&0xf) + (value&0xf) + (carry_result_ & Flag::Carry); + + // overflow for addition is when the signs were originally + // the same and the result is different + int overflow = ~(value^a_) & (result^a_); + + a_ = (uint8_t)result; + set_arithmetic_flags(0, result); + } break; + +#undef set_arithmetic_flags + + case MicroOp::NEG: { + int overflow = (a_ == 0x80); + int result = -a_; + int halfResult = -(a_&0xf); + + a_ = (uint8_t)result; + bit53_result_ = sign_result_ = zero_result_ = a_; + parity_overflow_result_ = overflow ? Flag::Overflow : 0; + subtract_flag_ = Flag::Subtract; + carry_result_ = (uint8_t)(result >> 8); + half_carry_result_ = (uint8_t)halfResult; + } break; + + case MicroOp::Increment8: { + uint8_t value = *(uint8_t *)operation->source; + int result = value + 1; + + // with an increment, overflow occurs if the sign changes from + // positive to negative + int overflow = (value ^ result) & ~value; + int half_result = (value&0xf) + 1; + + *(uint8_t *)operation->source = (uint8_t)result; + + // sign, zero and 5 & 3 are set directly from the result + bit53_result_ = sign_result_ = zero_result_ = (uint8_t)result; + half_carry_result_ = (uint8_t)half_result; + parity_overflow_result_ = (uint8_t)(overflow >> 5); + subtract_flag_ = 0; + } break; + + case MicroOp::Decrement8: { + uint8_t value = *(uint8_t *)operation->source; + int result = value - 1; + + // with a decrement, overflow occurs if the sign changes from + // negative to positive + int overflow = (value ^ result) & value; + int half_result = (value&0xf) - 1; + + *(uint8_t *)operation->source = (uint8_t)result; + + // sign, zero and 5 & 3 are set directly from the result + bit53_result_ = sign_result_ = zero_result_ = (uint8_t)result; + half_carry_result_ = (uint8_t)half_result; + parity_overflow_result_ = (uint8_t)(overflow >> 5); + subtract_flag_ = Flag::Subtract; + } break; + + case MicroOp::DAA: { + int lowNibble = a_ & 0xf; + int highNibble = a_ >> 4; + int amountToAdd = 0; + + if(carry_result_ & Flag::Carry) + { + amountToAdd = (lowNibble > 0x9 || (half_carry_result_ & Flag::HalfCarry)) ? 0x66 : 0x60; + } + else + { + if(half_carry_result_ & Flag::HalfCarry) + { + if(lowNibble > 0x9) + amountToAdd = (highNibble > 0x8) ? 0x66 : 0x06; + else + amountToAdd = (highNibble > 0x9) ? 0x66 : 0x06; + } + else + { + if(lowNibble > 0x9) + amountToAdd = (highNibble > 0x8) ? 0x66 : 0x06; + else + amountToAdd = (highNibble > 0x9) ? 0x60 : 0x00; + } + } + + if(!(carry_result_ & Flag::Carry)) + { + if(lowNibble > 0x9) + { + if(highNibble > 0x8) carry_result_ = Flag::Carry; + } + else + { + if(highNibble > 0x9) carry_result_ = Flag::Carry; + } + } + + if(subtract_flag_) + { + a_ -= amountToAdd; + half_carry_result_ = ((half_carry_result_ & Flag::HalfCarry) && lowNibble < 0x6) ? Flag::HalfCarry : 0; + } + else + { + a_ += amountToAdd; + half_carry_result_ = (lowNibble > 0x9) ? Flag::HalfCarry : 0; + } + + sign_result_ = zero_result_ = bit53_result_ = a_; + + set_parity(a_); + } break; + +#pragma mark - 16-bit arithmetic + + case MicroOp::ADD16: { + memptr_.full = *(uint16_t *)operation->destination; + uint16_t sourceValue = *(uint16_t *)operation->source; + uint16_t destinationValue = memptr_.full; + int result = sourceValue + destinationValue; + int halfResult = (sourceValue&0xfff) + (destinationValue&0xfff); + + bit53_result_ = (uint8_t)(result >> 8); + carry_result_ = (uint8_t)(result >> 16); + half_carry_result_ = (uint8_t)(halfResult >> 8); + subtract_flag_ = 0; + + *(uint16_t *)operation->destination = (uint16_t)result; + memptr_.full++; + } break; + + case MicroOp::ADC16: { + memptr_.full = *(uint16_t *)operation->destination; + uint16_t sourceValue = *(uint16_t *)operation->source; + uint16_t destinationValue = memptr_.full; + int result = sourceValue + destinationValue + (carry_result_ & Flag::Carry); + int halfResult = (sourceValue&0xfff) + (destinationValue&0xfff) + (carry_result_ & Flag::Carry); + + int overflow = (result ^ destinationValue) & ~(destinationValue ^ sourceValue); + + bit53_result_ = + sign_result_ = (uint8_t)(result >> 8); + zero_result_ = (uint8_t)(result | sign_result_); + subtract_flag_ = 0; + carry_result_ = (uint8_t)(result >> 16); + half_carry_result_ = (uint8_t)(halfResult >> 8); + parity_overflow_result_ = (uint8_t)(overflow >> 13); + + *(uint16_t *)operation->destination = (uint16_t)result; + memptr_.full++; + } break; + + case MicroOp::SBC16: { + memptr_.full = *(uint16_t *)operation->destination; + uint16_t sourceValue = *(uint16_t *)operation->source; + uint16_t destinationValue = memptr_.full; + int result = destinationValue - sourceValue - (carry_result_ & Flag::Carry); + int halfResult = (destinationValue&0xfff) - (sourceValue&0xfff) - (carry_result_ & Flag::Carry); + + // subtraction, so parity rules are: + // signs of operands were different, + // sign of result is different + int overflow = (result ^ destinationValue) & (sourceValue ^ destinationValue); + + bit53_result_ = + sign_result_ = (uint8_t)(result >> 8); + zero_result_ = (uint8_t)(result | sign_result_); + subtract_flag_ = Flag::Subtract; + carry_result_ = (uint8_t)(result >> 16); + half_carry_result_ = (uint8_t)(halfResult >> 8); + parity_overflow_result_ = (uint8_t)(overflow >> 13); + + *(uint16_t *)operation->destination = (uint16_t)result; + memptr_.full++; + } break; + +#pragma mark - Conditionals + +#define decline_conditional() \ + if(operation->source) { \ + scheduled_program_counter_ = (MicroOp *)operation->source; \ + } else { \ + advance_operation(); \ + } + + case MicroOp::TestNZ: if(!zero_result_) { decline_conditional(); } break; + case MicroOp::TestZ: if(zero_result_) { decline_conditional(); } break; + case MicroOp::TestNC: if(carry_result_ & Flag::Carry) { decline_conditional(); } break; + case MicroOp::TestC: if(!(carry_result_ & Flag::Carry)) { decline_conditional(); } break; + case MicroOp::TestPO: if(parity_overflow_result_ & Flag::Parity) { decline_conditional(); } break; + case MicroOp::TestPE: if(!(parity_overflow_result_ & Flag::Parity)) { decline_conditional(); } break; + case MicroOp::TestP: if(sign_result_ & Flag::Sign) { decline_conditional(); } break; + case MicroOp::TestM: if(!(sign_result_ & Flag::Sign)) { decline_conditional(); } break; + +#undef decline_conditional + +#pragma mark - Exchange + +#define swap(a, b) temp = a.full; a.full = b.full; b.full = temp; + + case MicroOp::ExDEHL: { + uint16_t temp; + swap(de_, hl_); + } break; + + case MicroOp::ExAFAFDash: { + uint8_t a = a_; + uint8_t f = get_flags(); + set_flags(afDash_.bytes.low); + a_ = afDash_.bytes.high; + afDash_.bytes.high = a; + afDash_.bytes.low = f; + } break; + + case MicroOp::EXX: { + uint16_t temp; + swap(de_, deDash_); + swap(bc_, bcDash_); + swap(hl_, hlDash_); + } break; + +#undef swap + +#pragma mark - Repetition + +#define REPEAT(test) \ + if(test) { \ + pc_.full -= 2; \ + } else { \ + advance_operation(); \ + } + +#define LDxR_STEP(dir) \ + bc_.full--; \ + de_.full += dir; \ + hl_.full += dir; \ + uint8_t sum = a_ + temp8_; \ + bit53_result_ = (uint8_t)((sum&0x8) | ((sum & 0x02) << 4)); \ + subtract_flag_ = 0; \ + half_carry_result_ = 0; \ + parity_overflow_result_ = bc_.full ? Flag::Parity : 0; + + case MicroOp::LDDR: { + LDxR_STEP(-1); + REPEAT(bc_.full); + } break; + + case MicroOp::LDIR: { + LDxR_STEP(1); + REPEAT(bc_.full); + } break; + + case MicroOp::LDD: { + LDxR_STEP(-1); + } break; + + case MicroOp::LDI: { + LDxR_STEP(1); + } break; + +#undef LDxR_STEP + +#define CPxR_STEP(dir) \ + hl_.full += dir; \ + bc_.full--; \ + \ + uint8_t result = a_ - temp8_; \ + uint8_t halfResult = (a_&0xf) - (temp8_&0xf); \ + \ + parity_overflow_result_ = bc_.full ? Flag::Parity : 0; \ + half_carry_result_ = halfResult; \ + subtract_flag_ = Flag::Subtract; \ + sign_result_ = zero_result_ = result; \ + \ + result -= (halfResult >> 4)&1; \ + bit53_result_ = (uint8_t)((result&0x8) | ((result&0x2) << 4)); \ + + case MicroOp::CPDR: { + CPxR_STEP(-1); + REPEAT(bc_.full && sign_result_); + } break; + + case MicroOp::CPIR: { + CPxR_STEP(1); + REPEAT(bc_.full && sign_result_); + } break; + + case MicroOp::CPD: { + memptr_.full--; + CPxR_STEP(-1); + } break; + + case MicroOp::CPI: { + memptr_.full++; + CPxR_STEP(1); + } break; + +#undef CPxR_STEP + +#define INxR_STEP(dir) \ + bc_.bytes.high--; \ + hl_.full += dir; \ + \ + sign_result_ = zero_result_ = bit53_result_ = bc_.bytes.high; \ + subtract_flag_ = (temp8_ >> 6) & Flag::Subtract; \ + \ + int next_bc = bc_.bytes.low + dir; \ + int summation = temp8_ + (next_bc&0xff); \ + \ + if(summation > 0xff) { \ + carry_result_ = Flag::Carry; \ + half_carry_result_ = Flag::HalfCarry; \ + } else { \ + carry_result_ = 0; \ + half_carry_result_ = 0; \ + } \ + \ + summation = (summation&7) ^ bc_.bytes.high; \ + set_parity(summation); + + case MicroOp::INDR: { + INxR_STEP(-1); + REPEAT(bc_.bytes.high); + } break; + + case MicroOp::INIR: { + INxR_STEP(1); + REPEAT(bc_.bytes.high); + } break; + + case MicroOp::IND: { + memptr_.full = bc_.full - 1; + INxR_STEP(-1); + } break; + + case MicroOp::INI: { + memptr_.full = bc_.full + 1; + INxR_STEP(1); + } break; + +#undef INxR_STEP + +#define OUTxR_STEP(dir) \ + bc_.bytes.high--; \ + hl_.full += dir; \ + \ + sign_result_ = zero_result_ = bit53_result_ = bc_.bytes.high; \ + subtract_flag_ = (temp8_ >> 6) & Flag::Subtract; \ + \ + int summation = temp8_ + hl_.bytes.low; \ + if(summation > 0xff) { \ + carry_result_ = Flag::Carry; \ + half_carry_result_ = Flag::HalfCarry; \ + } else { \ + carry_result_ = half_carry_result_ = 0; \ + } \ + \ + summation = (summation&7) ^ bc_.bytes.high; \ + set_parity(summation); + + case MicroOp::OUT_R: + REPEAT(bc_.bytes.high); + break; + + case MicroOp::OUTD: { + OUTxR_STEP(-1); + memptr_.full = bc_.full - 1; + } break; + + case MicroOp::OUTI: { + OUTxR_STEP(1); + memptr_.full = bc_.full + 1; + } break; + +#undef OUTxR_STEP + +#pragma mark - Bit Manipulation + + case MicroOp::BIT: { + uint8_t result = *(uint8_t *)operation->source & (1 << ((operation_ >> 3)&7)); + + if(current_instruction_page_->is_indexed || ((operation_&0x08) == 7)) { + bit53_result_ = memptr_.bytes.high; + } else { + bit53_result_ = *(uint8_t *)operation->source; + } + + sign_result_ = zero_result_ = result; + half_carry_result_ = Flag::HalfCarry; + subtract_flag_ = 0; + parity_overflow_result_ = result ? 0 : Flag::Parity; + } break; + + case MicroOp::RES: + *(uint8_t *)operation->source &= ~(1 << ((operation_ >> 3)&7)); + break; + + case MicroOp::SET: + *(uint8_t *)operation->source |= (1 << ((operation_ >> 3)&7)); + break; + +#pragma mark - Rotation and shifting + +#define set_rotate_flags() \ + bit53_result_ = a_; \ + carry_result_ = new_carry; \ + subtract_flag_ = half_carry_result_ = 0; + + case MicroOp::RLA: { + uint8_t new_carry = a_ >> 7; + a_ = (uint8_t)((a_ << 1) | (carry_result_ & Flag::Carry)); + set_rotate_flags(); + } break; + + case MicroOp::RRA: { + uint8_t new_carry = a_ & 1; + a_ = (uint8_t)((a_ >> 1) | (carry_result_ << 7)); + set_rotate_flags(); + } break; + + case MicroOp::RLCA: { + uint8_t new_carry = a_ >> 7; + a_ = (uint8_t)((a_ << 1) | new_carry); + set_rotate_flags(); + } break; + + case MicroOp::RRCA: { + uint8_t new_carry = a_ & 1; + a_ = (uint8_t)((a_ >> 1) | (new_carry << 7)); + set_rotate_flags(); + } break; + +#undef set_rotate_flags + +#define set_shift_flags() \ + sign_result_ = zero_result_ = bit53_result_ = *(uint8_t *)operation->source; \ + set_parity(sign_result_); \ + half_carry_result_ = 0; \ + subtract_flag_ = 0; + + case MicroOp::RLC: + carry_result_ = *(uint8_t *)operation->source >> 7; + *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source << 1) | carry_result_); + set_shift_flags(); + break; + + case MicroOp::RRC: + carry_result_ = *(uint8_t *)operation->source; + *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source >> 1) | (carry_result_ << 7)); + set_shift_flags(); + break; + + case MicroOp::RL: { + uint8_t next_carry = *(uint8_t *)operation->source >> 7; + *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source << 1) | (carry_result_ & Flag::Carry)); + carry_result_ = next_carry; + set_shift_flags(); + } break; + + case MicroOp::RR: { + uint8_t next_carry = *(uint8_t *)operation->source; + *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source >> 1) | (carry_result_ << 7)); + carry_result_ = next_carry; + set_shift_flags(); + } break; + + case MicroOp::SLA: + carry_result_ = *(uint8_t *)operation->source >> 7; + *(uint8_t *)operation->source = (uint8_t)(*(uint8_t *)operation->source << 1); + set_shift_flags(); + break; + + case MicroOp::SRA: + carry_result_ = *(uint8_t *)operation->source; + *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source >> 1) | (*(uint8_t *)operation->source & 0x80)); + set_shift_flags(); + break; + + case MicroOp::SLL: + carry_result_ = *(uint8_t *)operation->source >> 7; + *(uint8_t *)operation->source = (uint8_t)(*(uint8_t *)operation->source << 1) | 1; + set_shift_flags(); + break; + + case MicroOp::SRL: + carry_result_ = *(uint8_t *)operation->source; + *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source >> 1)); + set_shift_flags(); + break; + +#undef set_shift_flags + +#define set_decimal_rotate_flags() \ + subtract_flag_ = 0; \ + half_carry_result_ = 0; \ + set_parity(a_); \ + bit53_result_ = zero_result_ = sign_result_ = a_; + + case MicroOp::RRD: { + memptr_.full = hl_.full + 1; + uint8_t low_nibble = a_ & 0xf; + a_ = (a_ & 0xf0) | (temp8_ & 0xf); + temp8_ = (uint8_t)((temp8_ >> 4) | (low_nibble << 4)); + set_decimal_rotate_flags(); + } break; + + case MicroOp::RLD: { + memptr_.full = hl_.full + 1; + uint8_t low_nibble = a_ & 0xf; + a_ = (a_ & 0xf0) | (temp8_ >> 4); + temp8_ = (uint8_t)((temp8_ << 4) | low_nibble); + set_decimal_rotate_flags(); + } break; + +#undef set_decimal_rotate_flags + + +#pragma mark - Interrupt state + + case MicroOp::EI: + iff1_ = iff2_ = true; + if(irq_line_) request_status_ |= Interrupt::IRQ; + break; + + case MicroOp::DI: + iff1_ = iff2_ = false; + request_status_ &= ~Interrupt::IRQ; + break; + + case MicroOp::IM: + switch(operation_ & 0x18) { + case 0x00: interrupt_mode_ = 0; break; + case 0x08: interrupt_mode_ = 0; break; // IM 0/1 + case 0x10: interrupt_mode_ = 1; break; + case 0x18: interrupt_mode_ = 2; break; + } + break; + +#pragma mark - Input + + case MicroOp::SetInFlags: + subtract_flag_ = half_carry_result_ = 0; + sign_result_ = zero_result_ = bit53_result_ = *(uint8_t *)operation->source; + set_parity(sign_result_); + break; + + case MicroOp::SetAFlags: + subtract_flag_ = half_carry_result_ = 0; + parity_overflow_result_ = iff2_ ? Flag::Parity : 0; + sign_result_ = zero_result_ = bit53_result_ = a_; + break; + + case MicroOp::SetZero: + temp8_ = 0; + break; + +#pragma mark - Special-case Flow + + case MicroOp::BeginIRQMode0: + pc_increment_ = 0; // deliberate fallthrough + case MicroOp::BeginIRQ: + iff2_ = iff1_ = false; + request_status_ &= ~Interrupt::IRQ; + temp16_.full = 0x38; + break; + + case MicroOp::BeginNMI: + iff2_ = iff1_; + iff1_ = false; + request_status_ &= ~Interrupt::IRQ; + break; + + case MicroOp::JumpTo66: + pc_.full = 0x66; + break; + + case MicroOp::RETN: + iff1_ = iff2_; + if(irq_line_ && iff1_) request_status_ |= Interrupt::IRQ; + break; + + case MicroOp::HALT: + halt_mask_ = 0x00; + break; + +#pragma mark - Interrupt handling + + case MicroOp::Reset: + iff1_ = iff2_ = false; + interrupt_mode_ = 0; + pc_.full = 0; + sp_.full = 0xffff; + a_ = 0xff; + set_flags(0xff); + ir_.full = 0; + break; + +#pragma mark - Internal bookkeeping + + case MicroOp::SetInstructionPage: + current_instruction_page_ = (InstructionPage *)operation->source; + scheduled_program_counter_ = current_instruction_page_->fetch_decode_execute_data; + break; + + case MicroOp::CalculateIndexAddress: + memptr_.full = (uint16_t)(*(uint16_t *)operation->source + (int8_t)temp8_); + break; + + case MicroOp::IndexedPlaceHolder: + printf("Hit placeholder!!!\n"); + return; + } +#undef set_parity + } + + } +} + +template < class T, + bool uses_bus_request, + bool uses_wait_line> void Processor + ::set_bus_request_line(bool value) { + assert(uses_bus_request); + bus_request_line_ = value; +} + +template < class T, + bool uses_bus_request, + bool uses_wait_line> bool Processor + ::get_bus_request_line() { + return bus_request_line_; +} + +template < class T, + bool uses_bus_request, + bool uses_wait_line> void Processor + ::set_wait_line(bool value) { + assert(uses_wait_line); + wait_line_ = value; +} + +template < class T, + bool uses_bus_request, + bool uses_wait_line> bool Processor + ::get_wait_line() { + return wait_line_; +} + +template < class T, + bool uses_bus_request, + bool uses_wait_line> void Processor + ::assemble_page(InstructionPage &target, InstructionTable &table, bool add_offsets) { + size_t number_of_micro_ops = 0; + size_t lengths[256]; + + // Count number of micro-ops required. + for(int c = 0; c < 256; c++) { + size_t length = 0; + while(!isTerminal(table[c][length].type)) length++; + length++; + lengths[c] = length; + number_of_micro_ops += length; + } + + // Allocate a landing area. + std::vector operation_indices; + target.all_operations.reserve(number_of_micro_ops); + target.instructions.resize(256, nullptr); + + // Copy in all programs, recording where they go. + size_t destination = 0; + for(size_t c = 0; c < 256; c++) { + operation_indices.push_back(target.all_operations.size()); + for(size_t t = 0; t < lengths[c];) { + // Skip zero-length bus cycles. + if(table[c][t].type == MicroOp::BusOperation && table[c][t].machine_cycle.length.as_int() == 0) { + t++; + continue; + } + + // Skip optional waits if this instance doesn't use the wait line. + if(table[c][t].machine_cycle.was_requested && !uses_wait_line) { + t++; + continue; + } + + // If an index placeholder is hit then drop it, and if offsets aren't being added, + // then also drop the indexing that follows, which is assumed to be everything + // up to and including the next ::CalculateIndexAddress. Coupled to the INDEX() macro. + if(table[c][t].type == MicroOp::IndexedPlaceHolder) { + t++; + if(!add_offsets) { + while(table[c][t].type != MicroOp::CalculateIndexAddress) t++; + t++; + } + } + target.all_operations.emplace_back(table[c][t]); + destination++; + t++; + } + } + + // Since the vector won't change again, it's now safe to set pointers. + size_t c = 0; + for(size_t index : operation_indices) { + target.instructions[c] = &target.all_operations[index]; + c++; + } +} + +template < class T, + bool uses_bus_request, + bool uses_wait_line> void Processor + ::copy_program(const MicroOp *source, std::vector &destination) { + size_t length = 0; + while(!isTerminal(source[length].type)) length++; + size_t pointer = 0; + while(true) { + // TODO: This test is duplicated from assemble_page; can a better factoring be found? + // Skip optional waits if this instance doesn't use the wait line. + if(source[pointer].machine_cycle.was_requested && !uses_wait_line) { + pointer++; + continue; + } + + destination.emplace_back(source[pointer]); + if(isTerminal(source[pointer].type)) break; + pointer++; + } +} + +bool ProcessorBase::get_halt_line() { + return halt_mask_ == 0x00; +} + +void ProcessorBase::set_interrupt_line(bool value, HalfCycles offset) { + if(irq_line_ == value) return; + + // IRQ requests are level triggered and masked. + irq_line_ = value; + if(irq_line_ && iff1_) { + request_status_ |= Interrupt::IRQ; + } else { + request_status_ &= ~Interrupt::IRQ; + } + + // If this change happened at least one cycle ago then: (i) we're promised that this is a machine + // cycle per the contract on supplying an offset; and (ii) that means it happened before the lines + // were sampled. So adjust the most recent sample. + if(offset <= HalfCycles(-2)) { + last_request_status_ = (last_request_status_ & ~Interrupt::IRQ) | (request_status_ & Interrupt::IRQ); + } +} + +bool ProcessorBase::get_interrupt_line() { + return irq_line_; +} + +void ProcessorBase::set_non_maskable_interrupt_line(bool value, int offset) { + // NMIs are edge triggered and cannot be masked. + nmi_line_ = value; + if(value) { + request_status_ |= Interrupt::NMI; + if(offset < 0) { + last_request_status_ |= Interrupt::NMI; + } + } +} + +bool ProcessorBase::get_non_maskable_interrupt_line() { + return nmi_line_; +} + +void ProcessorBase::set_reset_line(bool value) { + // Reset requests are level triggered and cannot be masked. + if(value) request_status_ |= Interrupt::Reset; + else request_status_ &= ~Interrupt::Reset; +} diff --git a/Processors/Z80/Implementation/Z80Storage.hpp b/Processors/Z80/Implementation/Z80Storage.hpp new file mode 100644 index 000000000..ca9cc01e9 --- /dev/null +++ b/Processors/Z80/Implementation/Z80Storage.hpp @@ -0,0 +1,657 @@ +// +// Z80Storage.hpp +// Clock Signal +// +// Created by Thomas Harte on 01/09/2017. +// Copyright © 2017 Thomas Harte. All rights reserved. +// + +/*! + A repository for all the internal state of a CPU::Z80::Processor; extracted into a separate base + class in order to remove it from visibility within the main Z80.hpp. +*/ + +struct MicroOp { + enum Type { + BusOperation, + DecodeOperation, + DecodeOperationNoRChange, + MoveToNextProgram, + + Increment8, + Increment16, + Decrement8, + Decrement16, + Move8, + Move16, + + IncrementPC, + + AssembleAF, + DisassembleAF, + + And, + Or, + Xor, + + TestNZ, + TestZ, + TestNC, + TestC, + TestPO, + TestPE, + TestP, + TestM, + + ADD16, ADC16, SBC16, + CP8, SUB8, SBC8, ADD8, ADC8, + NEG, + + ExDEHL, ExAFAFDash, EXX, + + EI, DI, IM, + + LDI, LDIR, LDD, LDDR, + CPI, CPIR, CPD, CPDR, + INI, INIR, IND, INDR, + OUTI, OUTD, OUT_R, + + RLA, RLCA, RRA, RRCA, + RLC, RRC, RL, RR, + SLA, SRA, SLL, SRL, + RLD, RRD, + + SetInstructionPage, + CalculateIndexAddress, + + BeginNMI, + BeginIRQ, + BeginIRQMode0, + RETN, + JumpTo66, + HALT, + + DJNZ, + DAA, + CPL, + SCF, + CCF, + + RES, + BIT, + SET, + + CalculateRSTDestination, + + SetAFlags, + SetInFlags, + SetZero, + + IndexedPlaceHolder, + + Reset + }; + Type type; + void *source; + void *destination; + PartialMachineCycle machine_cycle; +}; + +struct InstructionPage { + std::vector instructions; + std::vector all_operations; + std::vector fetch_decode_execute; + MicroOp *fetch_decode_execute_data; + uint8_t r_step; + bool is_indexed; + + InstructionPage() : r_step(1), is_indexed(false) {} +}; + +typedef MicroOp InstructionTable[256][30]; + +// Elemental bus operations +#define ReadOpcodeStart() PartialMachineCycle(PartialMachineCycle::ReadOpcodeStart, HalfCycles(3), &pc_.full, &operation_, false) +#define ReadOpcodeWait(f) PartialMachineCycle(PartialMachineCycle::ReadOpcodeWait, HalfCycles(2), &pc_.full, &operation_, f) +#define ReadOpcodeEnd() PartialMachineCycle(PartialMachineCycle::ReadOpcode, HalfCycles(1), &pc_.full, &operation_, false) + +#define Refresh(len) PartialMachineCycle(PartialMachineCycle::Refresh, HalfCycles(len), &refresh_addr_.full, nullptr, false) + +#define ReadStart(addr, val) PartialMachineCycle(PartialMachineCycle::ReadStart, HalfCycles(3), &addr.full, &val, false) +#define ReadWait(l, addr, val, f) PartialMachineCycle(PartialMachineCycle::ReadWait, HalfCycles(l), &addr.full, &val, f) +#define ReadEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Read, HalfCycles(3), &addr.full, &val, false) + +#define WriteStart(addr, val) PartialMachineCycle(PartialMachineCycle::WriteStart,HalfCycles(3), &addr.full, &val, false) +#define WriteWait(l, addr, val, f) PartialMachineCycle(PartialMachineCycle::WriteWait, HalfCycles(l), &addr.full, &val, f) +#define WriteEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Write, HalfCycles(3), &addr.full, &val, false) + +#define InputStart(addr, val) PartialMachineCycle(PartialMachineCycle::InputStart, HalfCycles(3), &addr.full, &val, false) +#define InputWait(addr, val, f) PartialMachineCycle(PartialMachineCycle::InputWait, HalfCycles(2), &addr.full, &val, f) +#define InputEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Input, HalfCycles(3), &addr.full, &val, false) + +#define OutputStart(addr, val) PartialMachineCycle(PartialMachineCycle::OutputStart, HalfCycles(3), &addr.full, &val, false) +#define OutputWait(addr, val, f) PartialMachineCycle(PartialMachineCycle::OutputWait, HalfCycles(2), &addr.full, &val, f) +#define OutputEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Output, HalfCycles(3), &addr.full, &val, false) + +#define IntAckStart(length, val) PartialMachineCycle(PartialMachineCycle::InterruptStart, HalfCycles(length), nullptr, &val, false) +#define IntWait(val) PartialMachineCycle(PartialMachineCycle::InterruptWait, HalfCycles(2), nullptr, &val, true) +#define IntAckEnd(val) PartialMachineCycle(PartialMachineCycle::Interrupt, HalfCycles(3), nullptr, &val, false) + + +// A wrapper to express a bus operation as a micro-op +#define BusOp(op) {MicroOp::BusOperation, nullptr, nullptr, op} + +// Compound bus operations, as micro-ops +#define Read3(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(2, addr, val, true)), BusOp(ReadEnd(addr, val)) +#define Read4(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(2, addr, val, false)), BusOp(ReadWait(2, addr, val, true)), BusOp(ReadEnd(addr, val)) +#define Read5(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(4, addr, val, false)), BusOp(ReadWait(2, addr, val, true)), BusOp(ReadEnd(addr, val)) + +#define Write3(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(2, addr, val, true)), BusOp(WriteEnd(addr, val)) +#define Write5(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(4, addr, val, false)), BusOp(WriteWait(2, addr, val, true)), BusOp(WriteEnd(addr, val)) + +#define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val, false)), BusOp(InputWait(addr, val, true)), BusOp(InputEnd(addr, val)) +#define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val, false)), BusOp(OutputWait(addr, val, true)), BusOp(OutputEnd(addr, val)) +#define InternalOperation(len) {MicroOp::BusOperation, nullptr, nullptr, {PartialMachineCycle::Internal, HalfCycles(len), nullptr, nullptr, false}} + +/// A sequence is a series of micro-ops that ends in a move-to-next-program operation. +#define Sequence(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} } + +/// An instruction is the part of an instruction that follows instruction fetch; it should include two or more refresh cycles and then the work of the instruction. +#define Instr(r, ...) Sequence(BusOp(Refresh(r)), __VA_ARGS__) + +/// A standard instruction is one with the most normal timing: two cycles of refresh, then the work. +#define StdInstr(...) Instr(4, __VA_ARGS__) + +// Assumption made: those instructions that are rated with an opcode fetch greater than four cycles spend the extra time +// providing a lengthened refresh cycle. I assume this because the CPU doesn't have foresight and presumably spends the +// normal refresh time decoding. So if it gets to cycle four and realises it has two more cycles of work, I have assumed +// it simply maintains the refresh state for an extra two cycles. + +class ProcessorStorage { + protected: + ProcessorStorage(); + void install_default_instruction_set(); + + uint8_t a_; + RegisterPair bc_, de_, hl_; + RegisterPair afDash_, bcDash_, deDash_, hlDash_; + RegisterPair ix_, iy_, pc_, sp_; + RegisterPair ir_, refresh_addr_; + bool iff1_, iff2_; + int interrupt_mode_; + uint16_t pc_increment_; + uint8_t sign_result_; // the sign flag is set if the value in sign_result_ is negative + uint8_t zero_result_; // the zero flag is set if the value in zero_result_ is zero + uint8_t half_carry_result_; // the half-carry flag is set if bit 4 of half_carry_result_ is set + uint8_t bit53_result_; // the bit 3 and 5 flags are set if the corresponding bits of bit53_result_ are set + uint8_t parity_overflow_result_; // the parity/overflow flag is set if the corresponding bit of parity_overflow_result_ is set + uint8_t subtract_flag_; // contains a copy of the subtract flag in isolation + uint8_t carry_result_; // the carry flag is set if bit 0 of carry_result_ is set + uint8_t halt_mask_; + + HalfCycles number_of_cycles_; + + enum Interrupt: uint8_t { + IRQ = 0x01, + NMI = 0x02, + Reset = 0x04, + PowerOn = 0x08 + }; + uint8_t request_status_; + uint8_t last_request_status_; + bool irq_line_, nmi_line_; + bool bus_request_line_; + bool wait_line_; + + uint8_t operation_; + RegisterPair temp16_, memptr_; + uint8_t temp8_; + + const MicroOp *scheduled_program_counter_; + + std::vector conditional_call_untaken_program_; + std::vector reset_program_; + std::vector irq_program_[3]; + std::vector nmi_program_; + InstructionPage *current_instruction_page_; + + InstructionPage base_page_; + InstructionPage ed_page_; + InstructionPage fd_page_; + InstructionPage dd_page_; + + InstructionPage cb_page_; + InstructionPage fdcb_page_; + InstructionPage ddcb_page_; + + /*! + Gets the flags register. + + @see set_flags + + @returns The current value of the flags register. + */ + uint8_t get_flags() { + uint8_t result = + (sign_result_ & Flag::Sign) | + (zero_result_ ? 0 : Flag::Zero) | + (bit53_result_ & (Flag::Bit5 | Flag::Bit3)) | + (half_carry_result_ & Flag::HalfCarry) | + (parity_overflow_result_ & Flag::Parity) | + subtract_flag_ | + (carry_result_ & Flag::Carry); + return result; + } + + /*! + Sets the flags register. + + @see set_flags + + @param flags The new value of the flags register. + */ + void set_flags(uint8_t flags) { + sign_result_ = flags; + zero_result_ = (flags & Flag::Zero) ^ Flag::Zero; + bit53_result_ = flags; + half_carry_result_ = flags; + parity_overflow_result_ = flags; + subtract_flag_ = flags & Flag::Subtract; + carry_result_ = flags; + } + +/* The following are helper macros that define common parts of instructions */ +#define Inc16(r) {(&r == &pc_) ? MicroOp::IncrementPC : MicroOp::Increment16, &r.full} + +#define ReadInc(addr, val) Read3(addr, val), Inc16(addr) +#define Read4Inc(addr, val) Read4(addr, val), Inc16(addr) +#define Read5Inc(addr, val) Read5(addr, val), Inc16(addr) +#define WriteInc(addr, val) Write3(addr, val), {MicroOp::Increment16, &addr.full} + +#define Read16Inc(addr, val) ReadInc(addr, val.bytes.low), ReadInc(addr, val.bytes.high) +#define Read16(addr, val) ReadInc(addr, val.bytes.low), Read3(addr, val.bytes.high) + +#define Write16(addr, val) WriteInc(addr, val.bytes.low), Write3(addr, val.bytes.high) + +#define INDEX() {MicroOp::IndexedPlaceHolder}, ReadInc(pc_, temp8_), InternalOperation(10), {MicroOp::CalculateIndexAddress, &index} +#define FINDEX() {MicroOp::IndexedPlaceHolder}, ReadInc(pc_, temp8_), {MicroOp::CalculateIndexAddress, &index} +#define INDEX_ADDR() (add_offsets ? memptr_ : index) + +#define Push(x) {MicroOp::Decrement16, &sp_.full}, Write3(sp_, x.bytes.high), {MicroOp::Decrement16, &sp_.full}, Write3(sp_, x.bytes.low) +#define Pop(x) Read3(sp_, x.bytes.low), {MicroOp::Increment16, &sp_.full}, Read3(sp_, x.bytes.high), {MicroOp::Increment16, &sp_.full} + +#define Push8(x) {MicroOp::Decrement16, &sp_.full}, Write3(sp_, x.bytes.high), {MicroOp::Decrement16, &sp_.full}, Write5(sp_, x.bytes.low) +#define Pop7(x) Read3(sp_, x.bytes.low), {MicroOp::Increment16, &sp_.full}, Read4(sp_, x.bytes.high), {MicroOp::Increment16, &sp_.full} + +/* The following are actual instructions */ +#define NOP Sequence(BusOp(Refresh(4))) + +#define JP(cc) StdInstr(Read16Inc(pc_, temp16_), {MicroOp::cc, nullptr}, {MicroOp::Move16, &temp16_.full, &pc_.full}) +#define CALL(cc) StdInstr(ReadInc(pc_, temp16_.bytes.low), {MicroOp::cc, conditional_call_untaken_program_.data()}, Read4Inc(pc_, temp16_.bytes.high), Push(pc_), {MicroOp::Move16, &temp16_.full, &pc_.full}) +#define RET(cc) Instr(6, {MicroOp::cc, nullptr}, Pop(memptr_), {MicroOp::Move16, &memptr_.full, &pc_.full}) +#define JR(cc) StdInstr(ReadInc(pc_, temp8_), {MicroOp::cc, nullptr}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}) +#define RST() Instr(6, {MicroOp::CalculateRSTDestination}, Push(pc_), {MicroOp::Move16, &memptr_.full, &pc_.full}) +#define LD(a, b) StdInstr({MicroOp::Move8, &b, &a}) + +#define LD_GROUP(r, ri) \ + LD(r, bc_.bytes.high), LD(r, bc_.bytes.low), LD(r, de_.bytes.high), LD(r, de_.bytes.low), \ + LD(r, index.bytes.high), LD(r, index.bytes.low), \ + StdInstr(INDEX(), Read3(INDEX_ADDR(), temp8_), {MicroOp::Move8, &temp8_, &ri}), \ + LD(r, a_) + +#define READ_OP_GROUP(op) \ + StdInstr({MicroOp::op, &bc_.bytes.high}), StdInstr({MicroOp::op, &bc_.bytes.low}), \ + StdInstr({MicroOp::op, &de_.bytes.high}), StdInstr({MicroOp::op, &de_.bytes.low}), \ + StdInstr({MicroOp::op, &index.bytes.high}), StdInstr({MicroOp::op, &index.bytes.low}), \ + StdInstr(INDEX(), Read3(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ + StdInstr({MicroOp::op, &a_}) + +#define READ_OP_GROUP_D(op) \ + StdInstr({MicroOp::op, &bc_.bytes.high}), StdInstr({MicroOp::op, &bc_.bytes.low}), \ + StdInstr({MicroOp::op, &de_.bytes.high}), StdInstr({MicroOp::op, &de_.bytes.low}), \ + StdInstr({MicroOp::op, &index.bytes.high}), StdInstr({MicroOp::op, &index.bytes.low}), \ + StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ + StdInstr({MicroOp::op, &a_}) + +#define RMW(x, op, ...) StdInstr(INDEX(), Read4(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x)) +#define RMWI(x, op, ...) StdInstr(Read4(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x)) + +#define MODIFY_OP_GROUP(op) \ + StdInstr({MicroOp::op, &bc_.bytes.high}), StdInstr({MicroOp::op, &bc_.bytes.low}), \ + StdInstr({MicroOp::op, &de_.bytes.high}), StdInstr({MicroOp::op, &de_.bytes.low}), \ + StdInstr({MicroOp::op, &index.bytes.high}), StdInstr({MicroOp::op, &index.bytes.low}), \ + RMW(temp8_, op), \ + StdInstr({MicroOp::op, &a_}) + +#define IX_MODIFY_OP_GROUP(op) \ + RMWI(bc_.bytes.high, op), \ + RMWI(bc_.bytes.low, op), \ + RMWI(de_.bytes.high, op), \ + RMWI(de_.bytes.low, op), \ + RMWI(hl_.bytes.high, op), \ + RMWI(hl_.bytes.low, op), \ + RMWI(temp8_, op), \ + RMWI(a_, op) + +#define IX_READ_OP_GROUP(op) \ + StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ + StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ + StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ + StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ + StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ + StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ + StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ + StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}) + +#define ADD16(d, s) StdInstr(InternalOperation(8), InternalOperation(6), {MicroOp::ADD16, &s.full, &d.full}) +#define ADC16(d, s) StdInstr(InternalOperation(8), InternalOperation(6), {MicroOp::ADC16, &s.full, &d.full}) +#define SBC16(d, s) StdInstr(InternalOperation(8), InternalOperation(6), {MicroOp::SBC16, &s.full, &d.full}) + +#define isTerminal(n) (n == MicroOp::MoveToNextProgram || n == MicroOp::DecodeOperation || n == MicroOp::DecodeOperationNoRChange) + + virtual void assemble_page(InstructionPage &target, InstructionTable &table, bool add_offsets) = 0; + void assemble_ed_page(InstructionPage &target) { +#define IN_C(r) StdInstr(Input(bc_, r), {MicroOp::SetInFlags, &r}) +#define OUT_C(r) StdInstr(Output(bc_, r)) +#define IN_OUT(r) IN_C(r), OUT_C(r) + +#define NOP_ROW() NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP + InstructionTable ed_program_table = { + NOP_ROW(), /* 0x00 */ + NOP_ROW(), /* 0x10 */ + NOP_ROW(), /* 0x20 */ + NOP_ROW(), /* 0x30 */ + /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(bc_.bytes.high), + /* 0x42 SBC HL, BC */ SBC16(hl_, bc_), /* 0x43 LD (nn), BC */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, bc_)), + /* 0x44 NEG */ StdInstr({MicroOp::NEG}), /* 0x45 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), + /* 0x46 IM 0 */ StdInstr({MicroOp::IM}), /* 0x47 LD I, A */ Instr(6, {MicroOp::Move8, &a_, &ir_.bytes.high}), + /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(bc_.bytes.low), + /* 0x4a ADC HL, BC */ ADC16(hl_, bc_), /* 0x4b LD BC, (nn) */ StdInstr(Read16Inc(pc_, temp16_), Read16(temp16_, bc_)), + /* 0x4c NEG */ StdInstr({MicroOp::NEG}), /* 0x4d RETI */ StdInstr(Pop(pc_), {MicroOp::RETN}), + /* 0x4e IM 0/1 */ StdInstr({MicroOp::IM}), /* 0x4f LD R, A */ Instr(6, {MicroOp::Move8, &a_, &ir_.bytes.low}), + /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(de_.bytes.high), + /* 0x52 SBC HL, DE */ SBC16(hl_, de_), /* 0x53 LD (nn), DE */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, de_)), + /* 0x54 NEG */ StdInstr({MicroOp::NEG}), /* 0x55 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), + /* 0x56 IM 1 */ StdInstr({MicroOp::IM}), /* 0x57 LD A, I */ Instr(6, {MicroOp::Move8, &ir_.bytes.high, &a_}, {MicroOp::SetAFlags}), + /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(de_.bytes.low), + /* 0x5a ADC HL, DE */ ADC16(hl_, de_), /* 0x5b LD DE, (nn) */ StdInstr(Read16Inc(pc_, temp16_), Read16(temp16_, de_)), + /* 0x5c NEG */ StdInstr({MicroOp::NEG}), /* 0x5d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), + /* 0x5e IM 2 */ StdInstr({MicroOp::IM}), /* 0x5f LD A, R */ Instr(6, {MicroOp::Move8, &ir_.bytes.low, &a_}, {MicroOp::SetAFlags}), + /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(hl_.bytes.high), + /* 0x62 SBC HL, HL */ SBC16(hl_, hl_), /* 0x63 LD (nn), HL */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, hl_)), + /* 0x64 NEG */ StdInstr({MicroOp::NEG}), /* 0x65 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), + /* 0x66 IM 0 */ StdInstr({MicroOp::IM}), /* 0x67 RRD */ StdInstr(Read3(hl_, temp8_), InternalOperation(8), {MicroOp::RRD}, Write3(hl_, temp8_)), + /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(hl_.bytes.low), + /* 0x6a ADC HL, HL */ ADC16(hl_, hl_), /* 0x6b LD HL, (nn) */ StdInstr(Read16Inc(pc_, temp16_), Read16(temp16_, hl_)), + /* 0x6c NEG */ StdInstr({MicroOp::NEG}), /* 0x6d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), + /* 0x6e IM 0/1 */ StdInstr({MicroOp::IM}), /* 0x6f RLD */ StdInstr(Read3(hl_, temp8_), InternalOperation(8), {MicroOp::RLD}, Write3(hl_, temp8_)), + /* 0x70 IN (C) */ IN_C(temp8_), /* 0x71 OUT (C), 0 */ StdInstr({MicroOp::SetZero}, Output(bc_, temp8_)), + /* 0x72 SBC HL, SP */ SBC16(hl_, sp_), /* 0x73 LD (nn), SP */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, sp_)), + /* 0x74 NEG */ StdInstr({MicroOp::NEG}), /* 0x75 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), + /* 0x76 IM 1 */ StdInstr({MicroOp::IM}), /* 0x77 XX */ NOP, + /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(a_), + /* 0x7a ADC HL, SP */ ADC16(hl_, sp_), /* 0x7b LD SP, (nn) */ StdInstr(Read16Inc(pc_, temp16_), Read16(temp16_, sp_)), + /* 0x7c NEG */ StdInstr({MicroOp::NEG}), /* 0x7d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), + /* 0x7e IM 2 */ StdInstr({MicroOp::IM}), /* 0x7f XX */ NOP, + NOP_ROW(), /* 0x80 */ + NOP_ROW(), /* 0x90 */ + /* 0xa0 LDI */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDI}), + /* 0xa1 CPI */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPI}), + /* 0xa2 INI */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::INI}), + /* 0xa3 OTI */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTI}, Output(bc_, temp8_)), + NOP, NOP, NOP, NOP, + /* 0xa8 LDD */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDD}), + /* 0xa9 CPD */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPD}), + /* 0xaa IND */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::IND}), + /* 0xab OTD */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTD}, Output(bc_, temp8_)), + NOP, NOP, NOP, NOP, + /* 0xb0 LDIR */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDIR}, InternalOperation(10)), + /* 0xb1 CPIR */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPIR}, InternalOperation(10)), + /* 0xb2 INIR */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::INIR}, InternalOperation(10)), + /* 0xb3 OTIR */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTI}, Output(bc_, temp8_), {MicroOp::OUT_R}, InternalOperation(10)), + NOP, NOP, NOP, NOP, + /* 0xb8 LDDR */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDDR}, InternalOperation(10)), + /* 0xb9 CPDR */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPDR}, InternalOperation(10)), + /* 0xba INDR */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::INDR}, InternalOperation(10)), + /* 0xbb OTDR */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTD}, Output(bc_, temp8_), {MicroOp::OUT_R}, InternalOperation(10)), + NOP, NOP, NOP, NOP, + NOP_ROW(), /* 0xc0 */ + NOP_ROW(), /* 0xd0 */ + NOP_ROW(), /* 0xe0 */ + NOP_ROW(), /* 0xf0 */ + }; + assemble_page(target, ed_program_table, false); +#undef NOP_ROW + } + + void assemble_cb_page(InstructionPage &target, RegisterPair &index, bool add_offsets) { +#define OCTO_OP_GROUP(m, x) m(x), m(x), m(x), m(x), m(x), m(x), m(x), m(x) +#define CB_PAGE(m, p) m(RLC), m(RRC), m(RL), m(RR), m(SLA), m(SRA), m(SLL), m(SRL), OCTO_OP_GROUP(p, BIT), OCTO_OP_GROUP(m, RES), OCTO_OP_GROUP(m, SET) + + InstructionTable cb_program_table = { + /* 0x00 RLC B; 0x01 RLC C; 0x02 RLC D; 0x03 RLC E; 0x04 RLC H; 0x05 RLC L; 0x06 RLC (HL); 0x07 RLC A */ + /* 0x08 RRC B; 0x09 RRC C; 0x0a RRC D; 0x0b RRC E; 0x0c RRC H; 0x0d RRC L; 0x0e RRC (HL); 0x0f RRC A */ + /* 0x10 RL B; 0x11 RL C; 0x12 RL D; 0x13 RL E; 0x14 RL H; 0x15 RL L; 0x16 RL (HL); 0x17 RL A */ + /* 0x18 RR B; 0x99 RR C; 0x1a RR D; 0x1b RR E; 0x1c RR H; 0x1d RR L; 0x1e RR (HL); 0x1f RR A */ + /* 0x20 SLA B; 0x21 SLA C; 0x22 SLA D; 0x23 SLA E; 0x24 SLA H; 0x25 SLA L; 0x26 SLA (HL); 0x27 SLA A */ + /* 0x28 SRA B; 0x29 SRA C; 0x2a SRA D; 0x2b SRA E; 0x2c SRA H; 0x2d SRA L; 0x2e SRA (HL); 0x2f SRA A */ + /* 0x30 SLL B; 0x31 SLL C; 0x32 SLL D; 0x33 SLL E; 0x34 SLL H; 0x35 SLL L; 0x36 SLL (HL); 0x37 SLL A */ + /* 0x38 SRL B; 0x39 SRL C; 0x3a SRL D; 0x3b SRL E; 0x3c SRL H; 0x3d SRL L; 0x3e SRL (HL); 0x3f SRL A */ + /* 0x40 – 0x7f: BIT */ + /* 0x80 – 0xcf: RES */ + /* 0xd0 – 0xdf: SET */ + CB_PAGE(MODIFY_OP_GROUP, READ_OP_GROUP_D) + }; + InstructionTable offsets_cb_program_table = { + CB_PAGE(IX_MODIFY_OP_GROUP, IX_READ_OP_GROUP) + }; + assemble_page(target, add_offsets ? offsets_cb_program_table : cb_program_table, add_offsets); + +#undef OCTO_OP_GROUP +#undef CB_PAGE + } + + void assemble_base_page(InstructionPage &target, RegisterPair &index, bool add_offsets, InstructionPage &cb_page) { +#define INC_DEC_LD(r) \ + StdInstr({MicroOp::Increment8, &r}), \ + StdInstr({MicroOp::Decrement8, &r}), \ + StdInstr(ReadInc(pc_, r)) + +#define INC_INC_DEC_LD(rf, r) \ + Instr(8, {MicroOp::Increment16, &rf.full}), INC_DEC_LD(r) + +#define DEC_INC_DEC_LD(rf, r) \ + Instr(8, {MicroOp::Decrement16, &rf.full}), INC_DEC_LD(r) + + InstructionTable base_program_table = { + /* 0x00 NOP */ NOP, /* 0x01 LD BC, nn */ StdInstr(Read16Inc(pc_, bc_)), + /* 0x02 LD (BC), A */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Write3(memptr_, a_)), + + /* 0x03 INC BC; 0x04 INC B; 0x05 DEC B; 0x06 LD B, n */ + INC_INC_DEC_LD(bc_, bc_.bytes.high), + + /* 0x07 RLCA */ StdInstr({MicroOp::RLCA}), + /* 0x08 EX AF, AF' */ StdInstr({MicroOp::ExAFAFDash}), /* 0x09 ADD HL, BC */ ADD16(index, bc_), + /* 0x0a LD A, (BC) */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Read3(memptr_, a_), Inc16(memptr_)), + + /* 0x0b DEC BC; 0x0c INC C; 0x0d DEC C; 0x0e LD C, n */ + DEC_INC_DEC_LD(bc_, bc_.bytes.low), + + /* 0x0f RRCA */ StdInstr({MicroOp::RRCA}), + /* 0x10 DJNZ */ Instr(6, ReadInc(pc_, temp8_), {MicroOp::DJNZ}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}), + /* 0x11 LD DE, nn */ StdInstr(Read16Inc(pc_, de_)), + /* 0x12 LD (DE), A */ StdInstr({MicroOp::Move16, &de_.full, &memptr_.full}, Write3(memptr_, a_)), + + /* 0x13 INC DE; 0x14 INC D; 0x15 DEC D; 0x16 LD D, n */ + INC_INC_DEC_LD(de_, de_.bytes.high), + + /* 0x17 RLA */ StdInstr({MicroOp::RLA}), + /* 0x18 JR */ StdInstr(ReadInc(pc_, temp8_), InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}), + /* 0x19 ADD HL, DE */ ADD16(index, de_), + /* 0x1a LD A, (DE) */ StdInstr({MicroOp::Move16, &de_.full, &memptr_.full}, Read3(memptr_, a_), Inc16(memptr_)), + + /* 0x1b DEC DE; 0x1c INC E; 0x1d DEC E; 0x1e LD E, n */ + DEC_INC_DEC_LD(de_, de_.bytes.low), + + /* 0x1f RRA */ StdInstr({MicroOp::RRA}), + /* 0x20 JR NZ */ JR(TestNZ), /* 0x21 LD HL, nn */ StdInstr(Read16Inc(pc_, index)), + /* 0x22 LD (nn), HL */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, index)), + + /* 0x23 INC HL; 0x24 INC H; 0x25 DEC H; 0x26 LD H, n */ + INC_INC_DEC_LD(index, index.bytes.high), + + /* 0x27 DAA */ StdInstr({MicroOp::DAA}), + /* 0x28 JR Z */ JR(TestZ), /* 0x29 ADD HL, HL */ ADD16(index, index), + /* 0x2a LD HL, (nn) */ StdInstr(Read16Inc(pc_, temp16_), Read16(temp16_, index)), + + /* 0x2b DEC HL; 0x2c INC L; 0x2d DEC L; 0x2e LD L, n */ + DEC_INC_DEC_LD(index, index.bytes.low), + + /* 0x2f CPL */ StdInstr({MicroOp::CPL}), + /* 0x30 JR NC */ JR(TestNC), /* 0x31 LD SP, nn */ StdInstr(Read16Inc(pc_, sp_)), + /* 0x32 LD (nn), A */ StdInstr(Read16Inc(pc_, temp16_), Write3(temp16_, a_)), + /* 0x33 INC SP */ Instr(8, {MicroOp::Increment16, &sp_.full}), + /* 0x34 INC (HL) */ StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::Increment8, &temp8_}, Write3(INDEX_ADDR(), temp8_)), + /* 0x35 DEC (HL) */ StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::Decrement8, &temp8_}, Write3(INDEX_ADDR(), temp8_)), + /* 0x36 LD (HL), n */ StdInstr(ReadInc(pc_, temp8_), Write3(INDEX_ADDR(), temp8_)), + /* 0x37 SCF */ StdInstr({MicroOp::SCF}), + /* 0x38 JR C */ JR(TestC), + /* 0x39 ADD HL, SP */ ADD16(index, sp_), + /* 0x3a LD A, (nn) */ StdInstr(Read16Inc(pc_, memptr_), Read3(memptr_, a_), Inc16(memptr_)), + /* 0x3b DEC SP */ Instr(8, {MicroOp::Decrement16, &sp_.full}), + + /* 0x3c INC A; 0x3d DEC A; 0x3e LD A, n */ + INC_DEC_LD(a_), + + /* 0x3f CCF */ StdInstr({MicroOp::CCF}), + + /* 0x40 LD B, B; 0x41 LD B, C; 0x42 LD B, D; 0x43 LD B, E; 0x44 LD B, H; 0x45 LD B, L; 0x46 LD B, (HL); 0x47 LD B, A */ + LD_GROUP(bc_.bytes.high, bc_.bytes.high), + + /* 0x48 LD C, B; 0x49 LD C, C; 0x4a LD C, D; 0x4b LD C, E; 0x4c LD C, H; 0x4d LD C, L; 0x4e LD C, (HL); 0x4f LD C, A */ + LD_GROUP(bc_.bytes.low, bc_.bytes.low), + + /* 0x50 LD D, B; 0x51 LD D, C; 0x52 LD D, D; 0x53 LD D, E; 0x54 LD D, H; 0x55 LD D, L; 0x56 LD D, (HL); 0x57 LD D, A */ + LD_GROUP(de_.bytes.high, de_.bytes.high), + + /* 0x58 LD E, B; 0x59 LD E, C; 0x5a LD E, D; 0x5b LD E, E; 0x5c LD E, H; 0x5d LD E, L; 0x5e LD E, (HL); 0x5f LD E, A */ + LD_GROUP(de_.bytes.low, de_.bytes.low), + + /* 0x60 LD H, B; 0x61 LD H, C; 0x62 LD H, D; 0x63 LD H, E; 0x64 LD H, H; 0x65 LD H, L; 0x66 LD H, (HL); 0x67 LD H, A */ + LD_GROUP(index.bytes.high, hl_.bytes.high), + + /* 0x68 LD L, B; 0x69 LD L, C; 0x6a LD L, D; 0x6b LD L, E; 0x6c LD L, H; 0x6d LD H, L; 0x6e LD L, (HL); 0x6f LD L, A */ + LD_GROUP(index.bytes.low, hl_.bytes.low), + + /* 0x70 LD (HL), B */ StdInstr(INDEX(), Write3(INDEX_ADDR(), bc_.bytes.high)), + /* 0x71 LD (HL), C */ StdInstr(INDEX(), Write3(INDEX_ADDR(), bc_.bytes.low)), + /* 0x72 LD (HL), D */ StdInstr(INDEX(), Write3(INDEX_ADDR(), de_.bytes.high)), + /* 0x73 LD (HL), E */ StdInstr(INDEX(), Write3(INDEX_ADDR(), de_.bytes.low)), + /* 0x74 LD (HL), H */ StdInstr(INDEX(), Write3(INDEX_ADDR(), hl_.bytes.high)), // neither of these stores parts of the index register; + /* 0x75 LD (HL), L */ StdInstr(INDEX(), Write3(INDEX_ADDR(), hl_.bytes.low)), // they always store exactly H and L. + /* 0x76 HALT */ StdInstr({MicroOp::HALT}), + /* 0x77 LD (HL), A */ StdInstr(INDEX(), Write3(INDEX_ADDR(), a_)), + + /* 0x78 LD A, B; 0x79 LD A, C; 0x7a LD A, D; 0x7b LD A, E; 0x7c LD A, H; 0x7d LD A, L; 0x7e LD A, (HL); 0x7f LD A, A */ + LD_GROUP(a_, a_), + + /* 0x80 ADD B; 0x81 ADD C; 0x82 ADD D; 0x83 ADD E; 0x84 ADD H; 0x85 ADD L; 0x86 ADD (HL); 0x87 ADD A */ + READ_OP_GROUP(ADD8), + + /* 0x88 ADC B; 0x89 ADC C; 0x8a ADC D; 0x8b ADC E; 0x8c ADC H; 0x8d ADC L; 0x8e ADC (HL); 0x8f ADC A */ + READ_OP_GROUP(ADC8), + + /* 0x90 SUB B; 0x91 SUB C; 0x92 SUB D; 0x93 SUB E; 0x94 SUB H; 0x95 SUB L; 0x96 SUB (HL); 0x97 SUB A */ + READ_OP_GROUP(SUB8), + + /* 0x98 SBC B; 0x99 SBC C; 0x9a SBC D; 0x9b SBC E; 0x9c SBC H; 0x9d SBC L; 0x9e SBC (HL); 0x9f SBC A */ + READ_OP_GROUP(SBC8), + + /* 0xa0 AND B; 0xa1 AND C; 0xa2 AND D; 0xa3 AND E; 0xa4 AND H; 0xa5 AND L; 0xa6 AND (HL); 0xa7 AND A */ + READ_OP_GROUP(And), + + /* 0xa8 XOR B; 0xa9 XOR C; 0xaa XOR D; 0xab XOR E; 0xac XOR H; 0xad XOR L; 0xae XOR (HL); 0xaf XOR A */ + READ_OP_GROUP(Xor), + + /* 0xb0 OR B; 0xb1 OR C; 0xb2 OR D; 0xb3 OR E; 0xb4 OR H; 0xb5 OR L; 0xb6 OR (HL); 0xb7 OR A */ + READ_OP_GROUP(Or), + + /* 0xb8 CP B; 0xb9 CP C; 0xba CP D; 0xbb CP E; 0xbc CP H; 0xbd CP L; 0xbe CP (HL); 0xbf CP A */ + READ_OP_GROUP(CP8), + + /* 0xc0 RET NZ */ RET(TestNZ), /* 0xc1 POP BC */ StdInstr(Pop(bc_)), + /* 0xc2 JP NZ */ JP(TestNZ), /* 0xc3 JP nn */ StdInstr(Read16(pc_, temp16_), {MicroOp::Move16, &temp16_.full, &pc_.full}), + /* 0xc4 CALL NZ */ CALL(TestNZ), /* 0xc5 PUSH BC */ Instr(6, Push(bc_)), + /* 0xc6 ADD A, n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::ADD8, &temp8_}), + /* 0xc7 RST 00h */ RST(), + /* 0xc8 RET Z */ RET(TestZ), /* 0xc9 RET */ StdInstr(Pop(pc_)), + /* 0xca JP Z */ JP(TestZ), /* 0xcb [CB page] */StdInstr(FINDEX(), {MicroOp::SetInstructionPage, &cb_page}), + /* 0xcc CALL Z */ CALL(TestZ), /* 0xcd CALL */ StdInstr(ReadInc(pc_, temp16_.bytes.low), Read4Inc(pc_, temp16_.bytes.high), Push(pc_), {MicroOp::Move16, &temp16_.full, &pc_.full}), + /* 0xce ADC A, n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::ADC8, &temp8_}), + /* 0xcf RST 08h */ RST(), + /* 0xd0 RET NC */ RET(TestNC), /* 0xd1 POP DE */ StdInstr(Pop(de_)), + /* 0xd2 JP NC */ JP(TestNC), /* 0xd3 OUT (n), A */StdInstr(ReadInc(pc_, temp16_.bytes.low), {MicroOp::Move8, &a_, &temp16_.bytes.high}, Output(temp16_, a_)), + /* 0xd4 CALL NC */ CALL(TestNC), /* 0xd5 PUSH DE */ Instr(6, Push(de_)), + /* 0xd6 SUB n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::SUB8, &temp8_}), + /* 0xd7 RST 10h */ RST(), + /* 0xd8 RET C */ RET(TestC), /* 0xd9 EXX */ StdInstr({MicroOp::EXX}), + /* 0xda JP C */ JP(TestC), /* 0xdb IN A, (n) */StdInstr(ReadInc(pc_, temp16_.bytes.low), {MicroOp::Move8, &a_, &temp16_.bytes.high}, Input(temp16_, a_)), + /* 0xdc CALL C */ CALL(TestC), /* 0xdd [DD page] */StdInstr({MicroOp::SetInstructionPage, &dd_page_}), + /* 0xde SBC A, n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::SBC8, &temp8_}), + /* 0xdf RST 18h */ RST(), + /* 0xe0 RET PO */ RET(TestPO), /* 0xe1 POP HL */ StdInstr(Pop(index)), + /* 0xe2 JP PO */ JP(TestPO), /* 0xe3 EX (SP), HL */StdInstr(Pop7(memptr_), Push8(index), {MicroOp::Move16, &memptr_.full, &index.full}), + /* 0xe4 CALL PO */ CALL(TestPO), /* 0xe5 PUSH HL */ Instr(6, Push(index)), + /* 0xe6 AND n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::And, &temp8_}), + /* 0xe7 RST 20h */ RST(), + /* 0xe8 RET PE */ RET(TestPE), /* 0xe9 JP (HL) */ StdInstr({MicroOp::Move16, &index.full, &pc_.full}), + /* 0xea JP PE */ JP(TestPE), /* 0xeb EX DE, HL */StdInstr({MicroOp::ExDEHL}), + /* 0xec CALL PE */ CALL(TestPE), /* 0xed [ED page] */StdInstr({MicroOp::SetInstructionPage, &ed_page_}), + /* 0xee XOR n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::Xor, &temp8_}), + /* 0xef RST 28h */ RST(), + /* 0xf0 RET p */ RET(TestP), /* 0xf1 POP AF */ StdInstr(Pop(temp16_), {MicroOp::DisassembleAF}), + /* 0xf2 JP P */ JP(TestP), /* 0xf3 DI */ StdInstr({MicroOp::DI}), + /* 0xf4 CALL P */ CALL(TestP), /* 0xf5 PUSH AF */ Instr(6, {MicroOp::AssembleAF}, Push(temp16_)), + /* 0xf6 OR n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::Or, &temp8_}), + /* 0xf7 RST 30h */ RST(), + /* 0xf8 RET M */ RET(TestM), /* 0xf9 LD SP, HL */Instr(8, {MicroOp::Move16, &index.full, &sp_.full}), + /* 0xfa JP M */ JP(TestM), /* 0xfb EI */ StdInstr({MicroOp::EI}), + /* 0xfc CALL M */ CALL(TestM), /* 0xfd [FD page] */StdInstr({MicroOp::SetInstructionPage, &fd_page_}), + /* 0xfe CP n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::CP8, &temp8_}), + /* 0xff RST 38h */ RST(), + }; + + if(add_offsets) { + // The indexed version of 0x36 differs substantially from the non-indexed by building index calculation into + // the cycle that fetches the final operand. So patch in a different microprogram if building an indexed table. + InstructionTable copy_table = { + StdInstr(FINDEX(), Read5Inc(pc_, temp8_), Write3(INDEX_ADDR(), temp8_)) + }; + memcpy(&base_program_table[0x36], ©_table[0], sizeof(copy_table[0])); + } + + assemble_cb_page(cb_page, index, add_offsets); + assemble_page(target, base_program_table, add_offsets); + } + + void assemble_fetch_decode_execute(InstructionPage &target, int length) { + const MicroOp normal_fetch_decode_execute[] = { + BusOp(ReadOpcodeStart()), + BusOp(ReadOpcodeWait(true)), + BusOp(ReadOpcodeEnd()), + { MicroOp::DecodeOperation } + }; + const MicroOp short_fetch_decode_execute[] = { + BusOp(ReadOpcodeStart()), + BusOp(ReadOpcodeWait(false)), + BusOp(ReadOpcodeWait(true)), + BusOp(ReadOpcodeEnd()), + { MicroOp::DecodeOperation } + }; + copy_program((length == 4) ? normal_fetch_decode_execute : short_fetch_decode_execute, target.fetch_decode_execute); + target.fetch_decode_execute_data = target.fetch_decode_execute.data(); + } + + virtual void copy_program(const MicroOp *source, std::vector &destination) = 0; + +}; diff --git a/Processors/Z80/Z80.cpp b/Processors/Z80/Z80.cpp deleted file mode 100644 index 631702641..000000000 --- a/Processors/Z80/Z80.cpp +++ /dev/null @@ -1,9 +0,0 @@ -// -// Z80.cpp -// Clock Signal -// -// Created by Thomas Harte on 14/05/2017. -// Copyright © 2017 Thomas Harte. All rights reserved. -// - -#include "Z80.hpp" diff --git a/Processors/Z80/Z80.hpp b/Processors/Z80/Z80.hpp index f616b9d1c..c379c8192 100644 --- a/Processors/Z80/Z80.hpp +++ b/Processors/Z80/Z80.hpp @@ -10,10 +10,8 @@ #define Z80_hpp #include -#include -#include -#include #include +#include #include "../RegisterSizes.hpp" #include "../../ClockReceiver/ClockReceiver.hpp" @@ -48,7 +46,7 @@ enum Register { }; /* - Flags as defined on the Z80; can be used to decode the result of @c get_flags or to form a value for @c set_flags. + Flags as defined on the Z80; can be used to decode the result of getting or setting @c Flags. */ enum Flag: uint8_t { Sign = 0x80, @@ -63,8 +61,9 @@ enum Flag: uint8_t { }; /*! - Subclasses will be given the task of performing bus operations, allowing them to provide whatever interface they like - between a Z80 and the rest of the system. @c BusOperation lists the types of bus operation that may be requested. + Subclasses will be given the task of performing partial machine cycles, allowing them to provide whatever interface they like + between a Z80 and the rest of the system. @c PartialMachineCycle defines the information they will be handed for each unit + of execution. */ struct PartialMachineCycle { enum Operation { @@ -93,818 +92,150 @@ struct PartialMachineCycle { OutputStart, InterruptStart, }; + /// The operation being carried out by the Z80. See the various getters below for better classification. const Operation operation; + /// The length of this operation. const HalfCycles length; + /// The current value of the address bus. const uint16_t *const address; + /// If the Z80 is outputting to the data bus, a pointer to that value. Otherwise, a pointer to the lcoation where the current data bus value should be placed. uint8_t *const value; + /// @c true if this operation is occurring only because of an external request; @c false otherwise. const bool was_requested; + /*! + @returns @c true if the processor believes that the bus handler should actually do something with + the content of this PartialMachineCycle; @c false otherwise. + */ inline bool expects_action() const { return operation <= Operation::Interrupt; } + /*! + @returns @c true if this partial machine cycle completes one of the documented full machine cycles; + @c false otherwise. + */ inline bool is_terminal() const { return operation <= Operation::BusAcknowledge; } + /*! + @returns @c true if this partial machine cycle is a wait cycle; @c false otherwise. + */ inline bool is_wait() const { return operation >= Operation::ReadOpcodeWait && operation <= Operation::InterruptWait; } - PartialMachineCycle(const PartialMachineCycle &rhs) noexcept : - operation(rhs.operation), - length(rhs.length), - address(rhs.address), - value(rhs.value), - was_requested(rhs.was_requested) {} - PartialMachineCycle(Operation operation, HalfCycles length, uint16_t *address, uint8_t *value, bool was_requested) noexcept : - operation(operation), length(length), address(address), value(value), was_requested(was_requested) {} - PartialMachineCycle() noexcept : - operation(Internal), length(0), address(nullptr), value(nullptr), was_requested(false) {} + PartialMachineCycle(const PartialMachineCycle &rhs) noexcept; + PartialMachineCycle(Operation operation, HalfCycles length, uint16_t *address, uint8_t *value, bool was_requested) noexcept; + PartialMachineCycle() noexcept; }; +/*! + A class providing empty implementations of the methods a Z80 uses to access the bus. To wire the Z80 to a bus, + machines should subclass BusHandler and then declare a realisation of the Z80 template, suplying their bus + handler. +*/ class BusHandler { public: - void flush() {} + /*! + Announces that the Z80 has performed the partial machine cycle defined by @c cycle. + + @returns The number of additional HalfCycles that passed in objective time while this Z80 operation was ongoing. + On an archetypal machine this will be HalfCycles(0) but some architectures may choose not to clock the Z80 + during some periods or may impose wait states so predictably that it's more efficient just to add them + via this mechanism. + */ HalfCycles perform_machine_cycle(const PartialMachineCycle &cycle) { return HalfCycles(0); } + + /*! + Announces completion of all the cycles supplied to a .run_for request on the 6502. Intended to allow + bus handlers to perform any deferred output work. + */ + void flush() {} }; -// Elemental bus operations -#define ReadOpcodeStart() PartialMachineCycle(PartialMachineCycle::ReadOpcodeStart, HalfCycles(3), &pc_.full, &operation_, false) -#define ReadOpcodeWait(f) PartialMachineCycle(PartialMachineCycle::ReadOpcodeWait, HalfCycles(2), &pc_.full, &operation_, f) -#define ReadOpcodeEnd() PartialMachineCycle(PartialMachineCycle::ReadOpcode, HalfCycles(1), &pc_.full, &operation_, false) - -#define Refresh(len) PartialMachineCycle(PartialMachineCycle::Refresh, HalfCycles(len), &refresh_addr_.full, nullptr, false) - -#define ReadStart(addr, val) PartialMachineCycle(PartialMachineCycle::ReadStart, HalfCycles(3), &addr.full, &val, false) -#define ReadWait(l, addr, val, f) PartialMachineCycle(PartialMachineCycle::ReadWait, HalfCycles(l), &addr.full, &val, f) -#define ReadEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Read, HalfCycles(3), &addr.full, &val, false) - -#define WriteStart(addr, val) PartialMachineCycle(PartialMachineCycle::WriteStart,HalfCycles(3), &addr.full, &val, false) -#define WriteWait(l, addr, val, f) PartialMachineCycle(PartialMachineCycle::WriteWait, HalfCycles(l), &addr.full, &val, f) -#define WriteEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Write, HalfCycles(3), &addr.full, &val, false) - -#define InputStart(addr, val) PartialMachineCycle(PartialMachineCycle::InputStart, HalfCycles(3), &addr.full, &val, false) -#define InputWait(addr, val, f) PartialMachineCycle(PartialMachineCycle::InputWait, HalfCycles(2), &addr.full, &val, f) -#define InputEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Input, HalfCycles(3), &addr.full, &val, false) - -#define OutputStart(addr, val) PartialMachineCycle(PartialMachineCycle::OutputStart, HalfCycles(3), &addr.full, &val, false) -#define OutputWait(addr, val, f) PartialMachineCycle(PartialMachineCycle::OutputWait, HalfCycles(2), &addr.full, &val, f) -#define OutputEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Output, HalfCycles(3), &addr.full, &val, false) - -#define IntAckStart(length, val) PartialMachineCycle(PartialMachineCycle::InterruptStart, HalfCycles(length), nullptr, &val, false) -#define IntWait(val) PartialMachineCycle(PartialMachineCycle::InterruptWait, HalfCycles(2), nullptr, &val, true) -#define IntAckEnd(val) PartialMachineCycle(PartialMachineCycle::Interrupt, HalfCycles(3), nullptr, &val, false) - - -// A wrapper to express a bus operation as a micro-op -#define BusOp(op) {MicroOp::BusOperation, nullptr, nullptr, op} - -// Compound bus operations, as micro-ops -#define Read3(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(2, addr, val, true)), BusOp(ReadEnd(addr, val)) -#define Read4(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(2, addr, val, false)), BusOp(ReadWait(2, addr, val, true)), BusOp(ReadEnd(addr, val)) -#define Read5(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(4, addr, val, false)), BusOp(ReadWait(2, addr, val, true)), BusOp(ReadEnd(addr, val)) - -#define Write3(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(2, addr, val, true)), BusOp(WriteEnd(addr, val)) -#define Write5(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(4, addr, val, false)), BusOp(WriteWait(2, addr, val, true)), BusOp(WriteEnd(addr, val)) - -#define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val, false)), BusOp(InputWait(addr, val, true)), BusOp(InputEnd(addr, val)) -#define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val, false)), BusOp(OutputWait(addr, val, true)), BusOp(OutputEnd(addr, val)) -#define InternalOperation(len) {MicroOp::BusOperation, nullptr, nullptr, {PartialMachineCycle::Internal, HalfCycles(len), nullptr, nullptr, false}} - -/// A sequence is a series of micro-ops that ends in a move-to-next-program operation. -#define Sequence(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} } - -/// An instruction is the part of an instruction that follows instruction fetch; it should include two or more refresh cycles and then the work of the instruction. -#define Instr(r, ...) Sequence(BusOp(Refresh(r)), __VA_ARGS__) - -/// A standard instruction is one with the most normal timing: two cycles of refresh, then the work. -#define StdInstr(...) Instr(4, __VA_ARGS__) - -// Assumption made: those instructions that are rated with an opcode fetch greater than four cycles spend the extra time -// providing a lengthened refresh cycle. I assume this because the CPU doesn't have foresight and presumably spends the -// normal refresh time decoding. So if it gets to cycle four and realises it has two more cycles of work, I have assumed -// it simply maintains the refresh state for an extra two cycles. +#include "Implementation/Z80Storage.hpp" /*! - @abstact An abstract base class for emulation of a Z80 processor via the curiously recurring template pattern/f-bounded polymorphism. - - @discussion Subclasses should implement @c perform_machine_cycle in - order to provide the bus on which the Z80 operates and @c flush(), which is called upon completion of a continuous run - of cycles to allow a subclass to bring any on-demand activities up to date. + A base class from which the Z80 descends; separated for implementation reasons only. */ -template class Processor { - private: - T &bus_handler_; - - uint8_t a_; - RegisterPair bc_, de_, hl_; - RegisterPair afDash_, bcDash_, deDash_, hlDash_; - RegisterPair ix_, iy_, pc_, sp_; - RegisterPair ir_, refresh_addr_; - bool iff1_, iff2_; - int interrupt_mode_; - uint16_t pc_increment_; - uint8_t sign_result_; // the sign flag is set if the value in sign_result_ is negative - uint8_t zero_result_; // the zero flag is set if the value in zero_result_ is zero - uint8_t half_carry_result_; // the half-carry flag is set if bit 4 of half_carry_result_ is set - uint8_t bit53_result_; // the bit 3 and 5 flags are set if the corresponding bits of bit53_result_ are set - uint8_t parity_overflow_result_; // the parity/overflow flag is set if the corresponding bit of parity_overflow_result_ is set - uint8_t subtract_flag_; // contains a copy of the subtract flag in isolation - uint8_t carry_result_; // the carry flag is set if bit 0 of carry_result_ is set - uint8_t halt_mask_; - - HalfCycles number_of_cycles_; - - enum Interrupt: uint8_t { - IRQ = 0x01, - NMI = 0x02, - Reset = 0x04, - PowerOn = 0x08 - }; - uint8_t request_status_; - uint8_t last_request_status_; - bool irq_line_, nmi_line_; - bool bus_request_line_; - bool wait_line_; - - uint8_t operation_; - RegisterPair temp16_, memptr_; - uint8_t temp8_; - - struct MicroOp { - enum Type { - BusOperation, - DecodeOperation, - DecodeOperationNoRChange, - MoveToNextProgram, - - Increment8, - Increment16, - Decrement8, - Decrement16, - Move8, - Move16, - - IncrementPC, - - AssembleAF, - DisassembleAF, - - And, - Or, - Xor, - - TestNZ, - TestZ, - TestNC, - TestC, - TestPO, - TestPE, - TestP, - TestM, - - ADD16, ADC16, SBC16, - CP8, SUB8, SBC8, ADD8, ADC8, - NEG, - - ExDEHL, ExAFAFDash, EXX, - - EI, DI, IM, - - LDI, LDIR, LDD, LDDR, - CPI, CPIR, CPD, CPDR, - INI, INIR, IND, INDR, - OUTI, OUTD, OUT_R, - - RLA, RLCA, RRA, RRCA, - RLC, RRC, RL, RR, - SLA, SRA, SLL, SRL, - RLD, RRD, - - SetInstructionPage, - CalculateIndexAddress, - - BeginNMI, - BeginIRQ, - BeginIRQMode0, - RETN, - JumpTo66, - HALT, - - DJNZ, - DAA, - CPL, - SCF, - CCF, - - RES, - BIT, - SET, - - CalculateRSTDestination, - - SetAFlags, - SetInFlags, - SetZero, - - IndexedPlaceHolder, - - Reset - }; - Type type; - void *source; - void *destination; - PartialMachineCycle machine_cycle; - }; - const MicroOp *scheduled_program_counter_; - - struct InstructionPage { - std::vector instructions; - std::vector all_operations; - std::vector fetch_decode_execute; - MicroOp *fetch_decode_execute_data; - uint8_t r_step; - bool is_indexed; - - InstructionPage() : r_step(1), is_indexed(false) {} - }; - std::vector conditional_call_untaken_program_; - std::vector reset_program_; - std::vector irq_program_[3]; - std::vector nmi_program_; - InstructionPage *current_instruction_page_; - - InstructionPage base_page_; - InstructionPage ed_page_; - InstructionPage fd_page_; - InstructionPage dd_page_; - - InstructionPage cb_page_; - InstructionPage fdcb_page_; - InstructionPage ddcb_page_; - - -/* The following are helper macros that define common parts of instructions */ -#define Inc16(r) {(&r == &pc_) ? MicroOp::IncrementPC : MicroOp::Increment16, &r.full} - -#define ReadInc(addr, val) Read3(addr, val), Inc16(addr) -#define Read4Inc(addr, val) Read4(addr, val), Inc16(addr) -#define Read5Inc(addr, val) Read5(addr, val), Inc16(addr) -#define WriteInc(addr, val) Write3(addr, val), {MicroOp::Increment16, &addr.full} - -#define Read16Inc(addr, val) ReadInc(addr, val.bytes.low), ReadInc(addr, val.bytes.high) -#define Read16(addr, val) ReadInc(addr, val.bytes.low), Read3(addr, val.bytes.high) - -#define Write16(addr, val) WriteInc(addr, val.bytes.low), Write3(addr, val.bytes.high) - -#define INDEX() {MicroOp::IndexedPlaceHolder}, ReadInc(pc_, temp8_), InternalOperation(10), {MicroOp::CalculateIndexAddress, &index} -#define FINDEX() {MicroOp::IndexedPlaceHolder}, ReadInc(pc_, temp8_), {MicroOp::CalculateIndexAddress, &index} -#define INDEX_ADDR() (add_offsets ? memptr_ : index) - -#define Push(x) {MicroOp::Decrement16, &sp_.full}, Write3(sp_, x.bytes.high), {MicroOp::Decrement16, &sp_.full}, Write3(sp_, x.bytes.low) -#define Pop(x) Read3(sp_, x.bytes.low), {MicroOp::Increment16, &sp_.full}, Read3(sp_, x.bytes.high), {MicroOp::Increment16, &sp_.full} - -#define Push8(x) {MicroOp::Decrement16, &sp_.full}, Write3(sp_, x.bytes.high), {MicroOp::Decrement16, &sp_.full}, Write5(sp_, x.bytes.low) -#define Pop7(x) Read3(sp_, x.bytes.low), {MicroOp::Increment16, &sp_.full}, Read4(sp_, x.bytes.high), {MicroOp::Increment16, &sp_.full} - -/* The following are actual instructions */ -#define NOP Sequence(BusOp(Refresh(4))) - -#define JP(cc) StdInstr(Read16Inc(pc_, temp16_), {MicroOp::cc, nullptr}, {MicroOp::Move16, &temp16_.full, &pc_.full}) -#define CALL(cc) StdInstr(ReadInc(pc_, temp16_.bytes.low), {MicroOp::cc, conditional_call_untaken_program_.data()}, Read4Inc(pc_, temp16_.bytes.high), Push(pc_), {MicroOp::Move16, &temp16_.full, &pc_.full}) -#define RET(cc) Instr(6, {MicroOp::cc, nullptr}, Pop(memptr_), {MicroOp::Move16, &memptr_.full, &pc_.full}) -#define JR(cc) StdInstr(ReadInc(pc_, temp8_), {MicroOp::cc, nullptr}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}) -#define RST() Instr(6, {MicroOp::CalculateRSTDestination}, Push(pc_), {MicroOp::Move16, &memptr_.full, &pc_.full}) -#define LD(a, b) StdInstr({MicroOp::Move8, &b, &a}) - -#define LD_GROUP(r, ri) \ - LD(r, bc_.bytes.high), LD(r, bc_.bytes.low), LD(r, de_.bytes.high), LD(r, de_.bytes.low), \ - LD(r, index.bytes.high), LD(r, index.bytes.low), \ - StdInstr(INDEX(), Read3(INDEX_ADDR(), temp8_), {MicroOp::Move8, &temp8_, &ri}), \ - LD(r, a_) - -#define READ_OP_GROUP(op) \ - StdInstr({MicroOp::op, &bc_.bytes.high}), StdInstr({MicroOp::op, &bc_.bytes.low}), \ - StdInstr({MicroOp::op, &de_.bytes.high}), StdInstr({MicroOp::op, &de_.bytes.low}), \ - StdInstr({MicroOp::op, &index.bytes.high}), StdInstr({MicroOp::op, &index.bytes.low}), \ - StdInstr(INDEX(), Read3(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ - StdInstr({MicroOp::op, &a_}) - -#define READ_OP_GROUP_D(op) \ - StdInstr({MicroOp::op, &bc_.bytes.high}), StdInstr({MicroOp::op, &bc_.bytes.low}), \ - StdInstr({MicroOp::op, &de_.bytes.high}), StdInstr({MicroOp::op, &de_.bytes.low}), \ - StdInstr({MicroOp::op, &index.bytes.high}), StdInstr({MicroOp::op, &index.bytes.low}), \ - StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ - StdInstr({MicroOp::op, &a_}) - -#define RMW(x, op, ...) StdInstr(INDEX(), Read4(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x)) -#define RMWI(x, op, ...) StdInstr(Read4(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x)) - -#define MODIFY_OP_GROUP(op) \ - StdInstr({MicroOp::op, &bc_.bytes.high}), StdInstr({MicroOp::op, &bc_.bytes.low}), \ - StdInstr({MicroOp::op, &de_.bytes.high}), StdInstr({MicroOp::op, &de_.bytes.low}), \ - StdInstr({MicroOp::op, &index.bytes.high}), StdInstr({MicroOp::op, &index.bytes.low}), \ - RMW(temp8_, op), \ - StdInstr({MicroOp::op, &a_}) - -#define IX_MODIFY_OP_GROUP(op) \ - RMWI(bc_.bytes.high, op), \ - RMWI(bc_.bytes.low, op), \ - RMWI(de_.bytes.high, op), \ - RMWI(de_.bytes.low, op), \ - RMWI(hl_.bytes.high, op), \ - RMWI(hl_.bytes.low, op), \ - RMWI(temp8_, op), \ - RMWI(a_, op) - -#define IX_READ_OP_GROUP(op) \ - StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ - StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ - StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ - StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ - StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ - StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ - StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \ - StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}) - -#define ADD16(d, s) StdInstr(InternalOperation(8), InternalOperation(6), {MicroOp::ADD16, &s.full, &d.full}) -#define ADC16(d, s) StdInstr(InternalOperation(8), InternalOperation(6), {MicroOp::ADC16, &s.full, &d.full}) -#define SBC16(d, s) StdInstr(InternalOperation(8), InternalOperation(6), {MicroOp::SBC16, &s.full, &d.full}) - -#define isTerminal(n) (n == MicroOp::MoveToNextProgram || n == MicroOp::DecodeOperation || n == MicroOp::DecodeOperationNoRChange) - - typedef MicroOp InstructionTable[256][30]; - - void assemble_page(InstructionPage &target, InstructionTable &table, bool add_offsets) { - size_t number_of_micro_ops = 0; - size_t lengths[256]; - - // Count number of micro-ops required. - for(int c = 0; c < 256; c++) { - size_t length = 0; - while(!isTerminal(table[c][length].type)) length++; - length++; - lengths[c] = length; - number_of_micro_ops += length; - } - - // Allocate a landing area. - std::vector operation_indices; - target.all_operations.reserve(number_of_micro_ops); - target.instructions.resize(256, nullptr); - - // Copy in all programs, recording where they go. - size_t destination = 0; - for(size_t c = 0; c < 256; c++) { - operation_indices.push_back(target.all_operations.size()); - for(size_t t = 0; t < lengths[c];) { - // Skip zero-length bus cycles. - if(table[c][t].type == MicroOp::BusOperation && table[c][t].machine_cycle.length.as_int() == 0) { - t++; - continue; - } - - // Skip optional waits if this instance doesn't use the wait line. - if(table[c][t].machine_cycle.was_requested && !uses_wait_line) { - t++; - continue; - } - - // If an index placeholder is hit then drop it, and if offsets aren't being added, - // then also drop the indexing that follows, which is assumed to be everything - // up to and including the next ::CalculateIndexAddress. Coupled to the INDEX() macro. - if(table[c][t].type == MicroOp::IndexedPlaceHolder) { - t++; - if(!add_offsets) { - while(table[c][t].type != MicroOp::CalculateIndexAddress) t++; - t++; - } - } - target.all_operations.emplace_back(table[c][t]); - destination++; - t++; - } - } - - // Since the vector won't change again, it's now safe to set pointers. - size_t c = 0; - for(size_t index : operation_indices) { - target.instructions[c] = &target.all_operations[index]; - c++; - } - } - - void assemble_ed_page(InstructionPage &target) { -#define IN_C(r) StdInstr(Input(bc_, r), {MicroOp::SetInFlags, &r}) -#define OUT_C(r) StdInstr(Output(bc_, r)) -#define IN_OUT(r) IN_C(r), OUT_C(r) - -#define NOP_ROW() NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP - InstructionTable ed_program_table = { - NOP_ROW(), /* 0x00 */ - NOP_ROW(), /* 0x10 */ - NOP_ROW(), /* 0x20 */ - NOP_ROW(), /* 0x30 */ - /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(bc_.bytes.high), - /* 0x42 SBC HL, BC */ SBC16(hl_, bc_), /* 0x43 LD (nn), BC */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, bc_)), - /* 0x44 NEG */ StdInstr({MicroOp::NEG}), /* 0x45 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), - /* 0x46 IM 0 */ StdInstr({MicroOp::IM}), /* 0x47 LD I, A */ Instr(6, {MicroOp::Move8, &a_, &ir_.bytes.high}), - /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(bc_.bytes.low), - /* 0x4a ADC HL, BC */ ADC16(hl_, bc_), /* 0x4b LD BC, (nn) */ StdInstr(Read16Inc(pc_, temp16_), Read16(temp16_, bc_)), - /* 0x4c NEG */ StdInstr({MicroOp::NEG}), /* 0x4d RETI */ StdInstr(Pop(pc_), {MicroOp::RETN}), - /* 0x4e IM 0/1 */ StdInstr({MicroOp::IM}), /* 0x4f LD R, A */ Instr(6, {MicroOp::Move8, &a_, &ir_.bytes.low}), - /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(de_.bytes.high), - /* 0x52 SBC HL, DE */ SBC16(hl_, de_), /* 0x53 LD (nn), DE */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, de_)), - /* 0x54 NEG */ StdInstr({MicroOp::NEG}), /* 0x55 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), - /* 0x56 IM 1 */ StdInstr({MicroOp::IM}), /* 0x57 LD A, I */ Instr(6, {MicroOp::Move8, &ir_.bytes.high, &a_}, {MicroOp::SetAFlags}), - /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(de_.bytes.low), - /* 0x5a ADC HL, DE */ ADC16(hl_, de_), /* 0x5b LD DE, (nn) */ StdInstr(Read16Inc(pc_, temp16_), Read16(temp16_, de_)), - /* 0x5c NEG */ StdInstr({MicroOp::NEG}), /* 0x5d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), - /* 0x5e IM 2 */ StdInstr({MicroOp::IM}), /* 0x5f LD A, R */ Instr(6, {MicroOp::Move8, &ir_.bytes.low, &a_}, {MicroOp::SetAFlags}), - /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(hl_.bytes.high), - /* 0x62 SBC HL, HL */ SBC16(hl_, hl_), /* 0x63 LD (nn), HL */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, hl_)), - /* 0x64 NEG */ StdInstr({MicroOp::NEG}), /* 0x65 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), - /* 0x66 IM 0 */ StdInstr({MicroOp::IM}), /* 0x67 RRD */ StdInstr(Read3(hl_, temp8_), InternalOperation(8), {MicroOp::RRD}, Write3(hl_, temp8_)), - /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(hl_.bytes.low), - /* 0x6a ADC HL, HL */ ADC16(hl_, hl_), /* 0x6b LD HL, (nn) */ StdInstr(Read16Inc(pc_, temp16_), Read16(temp16_, hl_)), - /* 0x6c NEG */ StdInstr({MicroOp::NEG}), /* 0x6d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), - /* 0x6e IM 0/1 */ StdInstr({MicroOp::IM}), /* 0x6f RLD */ StdInstr(Read3(hl_, temp8_), InternalOperation(8), {MicroOp::RLD}, Write3(hl_, temp8_)), - /* 0x70 IN (C) */ IN_C(temp8_), /* 0x71 OUT (C), 0 */ StdInstr({MicroOp::SetZero}, Output(bc_, temp8_)), - /* 0x72 SBC HL, SP */ SBC16(hl_, sp_), /* 0x73 LD (nn), SP */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, sp_)), - /* 0x74 NEG */ StdInstr({MicroOp::NEG}), /* 0x75 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), - /* 0x76 IM 1 */ StdInstr({MicroOp::IM}), /* 0x77 XX */ NOP, - /* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(a_), - /* 0x7a ADC HL, SP */ ADC16(hl_, sp_), /* 0x7b LD SP, (nn) */ StdInstr(Read16Inc(pc_, temp16_), Read16(temp16_, sp_)), - /* 0x7c NEG */ StdInstr({MicroOp::NEG}), /* 0x7d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}), - /* 0x7e IM 2 */ StdInstr({MicroOp::IM}), /* 0x7f XX */ NOP, - NOP_ROW(), /* 0x80 */ - NOP_ROW(), /* 0x90 */ - /* 0xa0 LDI */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDI}), - /* 0xa1 CPI */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPI}), - /* 0xa2 INI */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::INI}), - /* 0xa3 OTI */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTI}, Output(bc_, temp8_)), - NOP, NOP, NOP, NOP, - /* 0xa8 LDD */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDD}), - /* 0xa9 CPD */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPD}), - /* 0xaa IND */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::IND}), - /* 0xab OTD */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTD}, Output(bc_, temp8_)), - NOP, NOP, NOP, NOP, - /* 0xb0 LDIR */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDIR}, InternalOperation(10)), - /* 0xb1 CPIR */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPIR}, InternalOperation(10)), - /* 0xb2 INIR */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::INIR}, InternalOperation(10)), - /* 0xb3 OTIR */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTI}, Output(bc_, temp8_), {MicroOp::OUT_R}, InternalOperation(10)), - NOP, NOP, NOP, NOP, - /* 0xb8 LDDR */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDDR}, InternalOperation(10)), - /* 0xb9 CPDR */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPDR}, InternalOperation(10)), - /* 0xba INDR */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::INDR}, InternalOperation(10)), - /* 0xbb OTDR */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTD}, Output(bc_, temp8_), {MicroOp::OUT_R}, InternalOperation(10)), - NOP, NOP, NOP, NOP, - NOP_ROW(), /* 0xc0 */ - NOP_ROW(), /* 0xd0 */ - NOP_ROW(), /* 0xe0 */ - NOP_ROW(), /* 0xf0 */ - }; - assemble_page(target, ed_program_table, false); -#undef NOP_ROW - } - - void assemble_cb_page(InstructionPage &target, RegisterPair &index, bool add_offsets) { -#define OCTO_OP_GROUP(m, x) m(x), m(x), m(x), m(x), m(x), m(x), m(x), m(x) -#define CB_PAGE(m, p) m(RLC), m(RRC), m(RL), m(RR), m(SLA), m(SRA), m(SLL), m(SRL), OCTO_OP_GROUP(p, BIT), OCTO_OP_GROUP(m, RES), OCTO_OP_GROUP(m, SET) - - InstructionTable cb_program_table = { - /* 0x00 RLC B; 0x01 RLC C; 0x02 RLC D; 0x03 RLC E; 0x04 RLC H; 0x05 RLC L; 0x06 RLC (HL); 0x07 RLC A */ - /* 0x08 RRC B; 0x09 RRC C; 0x0a RRC D; 0x0b RRC E; 0x0c RRC H; 0x0d RRC L; 0x0e RRC (HL); 0x0f RRC A */ - /* 0x10 RL B; 0x11 RL C; 0x12 RL D; 0x13 RL E; 0x14 RL H; 0x15 RL L; 0x16 RL (HL); 0x17 RL A */ - /* 0x18 RR B; 0x99 RR C; 0x1a RR D; 0x1b RR E; 0x1c RR H; 0x1d RR L; 0x1e RR (HL); 0x1f RR A */ - /* 0x20 SLA B; 0x21 SLA C; 0x22 SLA D; 0x23 SLA E; 0x24 SLA H; 0x25 SLA L; 0x26 SLA (HL); 0x27 SLA A */ - /* 0x28 SRA B; 0x29 SRA C; 0x2a SRA D; 0x2b SRA E; 0x2c SRA H; 0x2d SRA L; 0x2e SRA (HL); 0x2f SRA A */ - /* 0x30 SLL B; 0x31 SLL C; 0x32 SLL D; 0x33 SLL E; 0x34 SLL H; 0x35 SLL L; 0x36 SLL (HL); 0x37 SLL A */ - /* 0x38 SRL B; 0x39 SRL C; 0x3a SRL D; 0x3b SRL E; 0x3c SRL H; 0x3d SRL L; 0x3e SRL (HL); 0x3f SRL A */ - /* 0x40 – 0x7f: BIT */ - /* 0x80 – 0xcf: RES */ - /* 0xd0 – 0xdf: SET */ - CB_PAGE(MODIFY_OP_GROUP, READ_OP_GROUP_D) - }; - InstructionTable offsets_cb_program_table = { - CB_PAGE(IX_MODIFY_OP_GROUP, IX_READ_OP_GROUP) - }; - assemble_page(target, add_offsets ? offsets_cb_program_table : cb_program_table, add_offsets); - -#undef OCTO_OP_GROUP -#undef CB_PAGE - } - - void assemble_base_page(InstructionPage &target, RegisterPair &index, bool add_offsets, InstructionPage &cb_page) { -#define INC_DEC_LD(r) \ - StdInstr({MicroOp::Increment8, &r}), \ - StdInstr({MicroOp::Decrement8, &r}), \ - StdInstr(ReadInc(pc_, r)) - -#define INC_INC_DEC_LD(rf, r) \ - Instr(8, {MicroOp::Increment16, &rf.full}), INC_DEC_LD(r) - -#define DEC_INC_DEC_LD(rf, r) \ - Instr(8, {MicroOp::Decrement16, &rf.full}), INC_DEC_LD(r) - - InstructionTable base_program_table = { - /* 0x00 NOP */ NOP, /* 0x01 LD BC, nn */ StdInstr(Read16Inc(pc_, bc_)), - /* 0x02 LD (BC), A */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Write3(memptr_, a_)), - - /* 0x03 INC BC; 0x04 INC B; 0x05 DEC B; 0x06 LD B, n */ - INC_INC_DEC_LD(bc_, bc_.bytes.high), - - /* 0x07 RLCA */ StdInstr({MicroOp::RLCA}), - /* 0x08 EX AF, AF' */ StdInstr({MicroOp::ExAFAFDash}), /* 0x09 ADD HL, BC */ ADD16(index, bc_), - /* 0x0a LD A, (BC) */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Read3(memptr_, a_), Inc16(memptr_)), - - /* 0x0b DEC BC; 0x0c INC C; 0x0d DEC C; 0x0e LD C, n */ - DEC_INC_DEC_LD(bc_, bc_.bytes.low), - - /* 0x0f RRCA */ StdInstr({MicroOp::RRCA}), - /* 0x10 DJNZ */ Instr(6, ReadInc(pc_, temp8_), {MicroOp::DJNZ}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}), - /* 0x11 LD DE, nn */ StdInstr(Read16Inc(pc_, de_)), - /* 0x12 LD (DE), A */ StdInstr({MicroOp::Move16, &de_.full, &memptr_.full}, Write3(memptr_, a_)), - - /* 0x13 INC DE; 0x14 INC D; 0x15 DEC D; 0x16 LD D, n */ - INC_INC_DEC_LD(de_, de_.bytes.high), - - /* 0x17 RLA */ StdInstr({MicroOp::RLA}), - /* 0x18 JR */ StdInstr(ReadInc(pc_, temp8_), InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}), - /* 0x19 ADD HL, DE */ ADD16(index, de_), - /* 0x1a LD A, (DE) */ StdInstr({MicroOp::Move16, &de_.full, &memptr_.full}, Read3(memptr_, a_), Inc16(memptr_)), - - /* 0x1b DEC DE; 0x1c INC E; 0x1d DEC E; 0x1e LD E, n */ - DEC_INC_DEC_LD(de_, de_.bytes.low), - - /* 0x1f RRA */ StdInstr({MicroOp::RRA}), - /* 0x20 JR NZ */ JR(TestNZ), /* 0x21 LD HL, nn */ StdInstr(Read16Inc(pc_, index)), - /* 0x22 LD (nn), HL */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, index)), - - /* 0x23 INC HL; 0x24 INC H; 0x25 DEC H; 0x26 LD H, n */ - INC_INC_DEC_LD(index, index.bytes.high), - - /* 0x27 DAA */ StdInstr({MicroOp::DAA}), - /* 0x28 JR Z */ JR(TestZ), /* 0x29 ADD HL, HL */ ADD16(index, index), - /* 0x2a LD HL, (nn) */ StdInstr(Read16Inc(pc_, temp16_), Read16(temp16_, index)), - - /* 0x2b DEC HL; 0x2c INC L; 0x2d DEC L; 0x2e LD L, n */ - DEC_INC_DEC_LD(index, index.bytes.low), - - /* 0x2f CPL */ StdInstr({MicroOp::CPL}), - /* 0x30 JR NC */ JR(TestNC), /* 0x31 LD SP, nn */ StdInstr(Read16Inc(pc_, sp_)), - /* 0x32 LD (nn), A */ StdInstr(Read16Inc(pc_, temp16_), Write3(temp16_, a_)), - /* 0x33 INC SP */ Instr(8, {MicroOp::Increment16, &sp_.full}), - /* 0x34 INC (HL) */ StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::Increment8, &temp8_}, Write3(INDEX_ADDR(), temp8_)), - /* 0x35 DEC (HL) */ StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::Decrement8, &temp8_}, Write3(INDEX_ADDR(), temp8_)), - /* 0x36 LD (HL), n */ StdInstr(ReadInc(pc_, temp8_), Write3(INDEX_ADDR(), temp8_)), - /* 0x37 SCF */ StdInstr({MicroOp::SCF}), - /* 0x38 JR C */ JR(TestC), - /* 0x39 ADD HL, SP */ ADD16(index, sp_), - /* 0x3a LD A, (nn) */ StdInstr(Read16Inc(pc_, memptr_), Read3(memptr_, a_), Inc16(memptr_)), - /* 0x3b DEC SP */ Instr(8, {MicroOp::Decrement16, &sp_.full}), - - /* 0x3c INC A; 0x3d DEC A; 0x3e LD A, n */ - INC_DEC_LD(a_), - - /* 0x3f CCF */ StdInstr({MicroOp::CCF}), - - /* 0x40 LD B, B; 0x41 LD B, C; 0x42 LD B, D; 0x43 LD B, E; 0x44 LD B, H; 0x45 LD B, L; 0x46 LD B, (HL); 0x47 LD B, A */ - LD_GROUP(bc_.bytes.high, bc_.bytes.high), - - /* 0x48 LD C, B; 0x49 LD C, C; 0x4a LD C, D; 0x4b LD C, E; 0x4c LD C, H; 0x4d LD C, L; 0x4e LD C, (HL); 0x4f LD C, A */ - LD_GROUP(bc_.bytes.low, bc_.bytes.low), - - /* 0x50 LD D, B; 0x51 LD D, C; 0x52 LD D, D; 0x53 LD D, E; 0x54 LD D, H; 0x55 LD D, L; 0x56 LD D, (HL); 0x57 LD D, A */ - LD_GROUP(de_.bytes.high, de_.bytes.high), - - /* 0x58 LD E, B; 0x59 LD E, C; 0x5a LD E, D; 0x5b LD E, E; 0x5c LD E, H; 0x5d LD E, L; 0x5e LD E, (HL); 0x5f LD E, A */ - LD_GROUP(de_.bytes.low, de_.bytes.low), - - /* 0x60 LD H, B; 0x61 LD H, C; 0x62 LD H, D; 0x63 LD H, E; 0x64 LD H, H; 0x65 LD H, L; 0x66 LD H, (HL); 0x67 LD H, A */ - LD_GROUP(index.bytes.high, hl_.bytes.high), - - /* 0x68 LD L, B; 0x69 LD L, C; 0x6a LD L, D; 0x6b LD L, E; 0x6c LD L, H; 0x6d LD H, L; 0x6e LD L, (HL); 0x6f LD L, A */ - LD_GROUP(index.bytes.low, hl_.bytes.low), - - /* 0x70 LD (HL), B */ StdInstr(INDEX(), Write3(INDEX_ADDR(), bc_.bytes.high)), - /* 0x71 LD (HL), C */ StdInstr(INDEX(), Write3(INDEX_ADDR(), bc_.bytes.low)), - /* 0x72 LD (HL), D */ StdInstr(INDEX(), Write3(INDEX_ADDR(), de_.bytes.high)), - /* 0x73 LD (HL), E */ StdInstr(INDEX(), Write3(INDEX_ADDR(), de_.bytes.low)), - /* 0x74 LD (HL), H */ StdInstr(INDEX(), Write3(INDEX_ADDR(), hl_.bytes.high)), // neither of these stores parts of the index register; - /* 0x75 LD (HL), L */ StdInstr(INDEX(), Write3(INDEX_ADDR(), hl_.bytes.low)), // they always store exactly H and L. - /* 0x76 HALT */ StdInstr({MicroOp::HALT}), - /* 0x77 LD (HL), A */ StdInstr(INDEX(), Write3(INDEX_ADDR(), a_)), - - /* 0x78 LD A, B; 0x79 LD A, C; 0x7a LD A, D; 0x7b LD A, E; 0x7c LD A, H; 0x7d LD A, L; 0x7e LD A, (HL); 0x7f LD A, A */ - LD_GROUP(a_, a_), - - /* 0x80 ADD B; 0x81 ADD C; 0x82 ADD D; 0x83 ADD E; 0x84 ADD H; 0x85 ADD L; 0x86 ADD (HL); 0x87 ADD A */ - READ_OP_GROUP(ADD8), - - /* 0x88 ADC B; 0x89 ADC C; 0x8a ADC D; 0x8b ADC E; 0x8c ADC H; 0x8d ADC L; 0x8e ADC (HL); 0x8f ADC A */ - READ_OP_GROUP(ADC8), - - /* 0x90 SUB B; 0x91 SUB C; 0x92 SUB D; 0x93 SUB E; 0x94 SUB H; 0x95 SUB L; 0x96 SUB (HL); 0x97 SUB A */ - READ_OP_GROUP(SUB8), - - /* 0x98 SBC B; 0x99 SBC C; 0x9a SBC D; 0x9b SBC E; 0x9c SBC H; 0x9d SBC L; 0x9e SBC (HL); 0x9f SBC A */ - READ_OP_GROUP(SBC8), - - /* 0xa0 AND B; 0xa1 AND C; 0xa2 AND D; 0xa3 AND E; 0xa4 AND H; 0xa5 AND L; 0xa6 AND (HL); 0xa7 AND A */ - READ_OP_GROUP(And), - - /* 0xa8 XOR B; 0xa9 XOR C; 0xaa XOR D; 0xab XOR E; 0xac XOR H; 0xad XOR L; 0xae XOR (HL); 0xaf XOR A */ - READ_OP_GROUP(Xor), - - /* 0xb0 OR B; 0xb1 OR C; 0xb2 OR D; 0xb3 OR E; 0xb4 OR H; 0xb5 OR L; 0xb6 OR (HL); 0xb7 OR A */ - READ_OP_GROUP(Or), - - /* 0xb8 CP B; 0xb9 CP C; 0xba CP D; 0xbb CP E; 0xbc CP H; 0xbd CP L; 0xbe CP (HL); 0xbf CP A */ - READ_OP_GROUP(CP8), - - /* 0xc0 RET NZ */ RET(TestNZ), /* 0xc1 POP BC */ StdInstr(Pop(bc_)), - /* 0xc2 JP NZ */ JP(TestNZ), /* 0xc3 JP nn */ StdInstr(Read16(pc_, temp16_), {MicroOp::Move16, &temp16_.full, &pc_.full}), - /* 0xc4 CALL NZ */ CALL(TestNZ), /* 0xc5 PUSH BC */ Instr(6, Push(bc_)), - /* 0xc6 ADD A, n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::ADD8, &temp8_}), - /* 0xc7 RST 00h */ RST(), - /* 0xc8 RET Z */ RET(TestZ), /* 0xc9 RET */ StdInstr(Pop(pc_)), - /* 0xca JP Z */ JP(TestZ), /* 0xcb [CB page] */StdInstr(FINDEX(), {MicroOp::SetInstructionPage, &cb_page}), - /* 0xcc CALL Z */ CALL(TestZ), /* 0xcd CALL */ StdInstr(ReadInc(pc_, temp16_.bytes.low), Read4Inc(pc_, temp16_.bytes.high), Push(pc_), {MicroOp::Move16, &temp16_.full, &pc_.full}), - /* 0xce ADC A, n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::ADC8, &temp8_}), - /* 0xcf RST 08h */ RST(), - /* 0xd0 RET NC */ RET(TestNC), /* 0xd1 POP DE */ StdInstr(Pop(de_)), - /* 0xd2 JP NC */ JP(TestNC), /* 0xd3 OUT (n), A */StdInstr(ReadInc(pc_, temp16_.bytes.low), {MicroOp::Move8, &a_, &temp16_.bytes.high}, Output(temp16_, a_)), - /* 0xd4 CALL NC */ CALL(TestNC), /* 0xd5 PUSH DE */ Instr(6, Push(de_)), - /* 0xd6 SUB n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::SUB8, &temp8_}), - /* 0xd7 RST 10h */ RST(), - /* 0xd8 RET C */ RET(TestC), /* 0xd9 EXX */ StdInstr({MicroOp::EXX}), - /* 0xda JP C */ JP(TestC), /* 0xdb IN A, (n) */StdInstr(ReadInc(pc_, temp16_.bytes.low), {MicroOp::Move8, &a_, &temp16_.bytes.high}, Input(temp16_, a_)), - /* 0xdc CALL C */ CALL(TestC), /* 0xdd [DD page] */StdInstr({MicroOp::SetInstructionPage, &dd_page_}), - /* 0xde SBC A, n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::SBC8, &temp8_}), - /* 0xdf RST 18h */ RST(), - /* 0xe0 RET PO */ RET(TestPO), /* 0xe1 POP HL */ StdInstr(Pop(index)), - /* 0xe2 JP PO */ JP(TestPO), /* 0xe3 EX (SP), HL */StdInstr(Pop7(memptr_), Push8(index), {MicroOp::Move16, &memptr_.full, &index.full}), - /* 0xe4 CALL PO */ CALL(TestPO), /* 0xe5 PUSH HL */ Instr(6, Push(index)), - /* 0xe6 AND n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::And, &temp8_}), - /* 0xe7 RST 20h */ RST(), - /* 0xe8 RET PE */ RET(TestPE), /* 0xe9 JP (HL) */ StdInstr({MicroOp::Move16, &index.full, &pc_.full}), - /* 0xea JP PE */ JP(TestPE), /* 0xeb EX DE, HL */StdInstr({MicroOp::ExDEHL}), - /* 0xec CALL PE */ CALL(TestPE), /* 0xed [ED page] */StdInstr({MicroOp::SetInstructionPage, &ed_page_}), - /* 0xee XOR n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::Xor, &temp8_}), - /* 0xef RST 28h */ RST(), - /* 0xf0 RET p */ RET(TestP), /* 0xf1 POP AF */ StdInstr(Pop(temp16_), {MicroOp::DisassembleAF}), - /* 0xf2 JP P */ JP(TestP), /* 0xf3 DI */ StdInstr({MicroOp::DI}), - /* 0xf4 CALL P */ CALL(TestP), /* 0xf5 PUSH AF */ Instr(6, {MicroOp::AssembleAF}, Push(temp16_)), - /* 0xf6 OR n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::Or, &temp8_}), - /* 0xf7 RST 30h */ RST(), - /* 0xf8 RET M */ RET(TestM), /* 0xf9 LD SP, HL */Instr(8, {MicroOp::Move16, &index.full, &sp_.full}), - /* 0xfa JP M */ JP(TestM), /* 0xfb EI */ StdInstr({MicroOp::EI}), - /* 0xfc CALL M */ CALL(TestM), /* 0xfd [FD page] */StdInstr({MicroOp::SetInstructionPage, &fd_page_}), - /* 0xfe CP n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::CP8, &temp8_}), - /* 0xff RST 38h */ RST(), - }; - - if(add_offsets) { - // The indexed version of 0x36 differs substantially from the non-indexed by building index calculation into - // the cycle that fetches the final operand. So patch in a different microprogram if building an indexed table. - InstructionTable copy_table = { - StdInstr(FINDEX(), Read5Inc(pc_, temp8_), Write3(INDEX_ADDR(), temp8_)) - }; - memcpy(&base_program_table[0x36], ©_table[0], sizeof(copy_table[0])); - } - - assemble_cb_page(cb_page, index, add_offsets); - assemble_page(target, base_program_table, add_offsets); - } - - void assemble_fetch_decode_execute(InstructionPage &target, int length) { - const MicroOp normal_fetch_decode_execute[] = { - BusOp(ReadOpcodeStart()), - BusOp(ReadOpcodeWait(true)), - BusOp(ReadOpcodeEnd()), - { MicroOp::DecodeOperation } - }; - const MicroOp short_fetch_decode_execute[] = { - BusOp(ReadOpcodeStart()), - BusOp(ReadOpcodeWait(false)), - BusOp(ReadOpcodeWait(true)), - BusOp(ReadOpcodeEnd()), - { MicroOp::DecodeOperation } - }; - copy_program((length == 4) ? normal_fetch_decode_execute : short_fetch_decode_execute, target.fetch_decode_execute); - target.fetch_decode_execute_data = target.fetch_decode_execute.data(); - } - - void copy_program(const MicroOp *source, std::vector &destination) { - size_t length = 0; - while(!isTerminal(source[length].type)) length++; - size_t pointer = 0; - while(true) { - // TODO: This test is duplicated from assemble_page; can a better factoring be found? - // Skip optional waits if this instance doesn't use the wait line. - if(source[pointer].machine_cycle.was_requested && !uses_wait_line) { - pointer++; - continue; - } - - destination.emplace_back(source[pointer]); - if(isTerminal(source[pointer].type)) break; - pointer++; - } - } - +class ProcessorBase: public ProcessorStorage { public: - Processor(T &bus_handler) : - halt_mask_(0xff), - interrupt_mode_(0), - wait_line_(false), - request_status_(Interrupt::PowerOn), - last_request_status_(Interrupt::PowerOn), - irq_line_(false), - nmi_line_(false), - bus_request_line_(false), - pc_increment_(1), - scheduled_program_counter_(nullptr), - bus_handler_(bus_handler) { - set_flags(0xff); + /*! + Gets the value of a register. - MicroOp conditional_call_untaken_program[] = Sequence(ReadInc(pc_, temp16_.bytes.high)); - copy_program(conditional_call_untaken_program, conditional_call_untaken_program_); + @see set_value_of_register - assemble_base_page(base_page_, hl_, false, cb_page_); - assemble_base_page(dd_page_, ix_, true, ddcb_page_); - assemble_base_page(fd_page_, iy_, true, fdcb_page_); - assemble_ed_page(ed_page_); + @param r The register to set. + @returns The value of the register. 8-bit registers will be returned as unsigned. + */ + uint16_t get_value_of_register(Register r); - fdcb_page_.r_step = 0; - fd_page_.is_indexed = true; - fdcb_page_.is_indexed = true; + /*! + Sets the value of a register. - ddcb_page_.r_step = 0; - dd_page_.is_indexed = true; - ddcb_page_.is_indexed = true; + @see get_value_of_register - assemble_fetch_decode_execute(base_page_, 4); - assemble_fetch_decode_execute(dd_page_, 4); - assemble_fetch_decode_execute(fd_page_, 4); - assemble_fetch_decode_execute(ed_page_, 4); - assemble_fetch_decode_execute(cb_page_, 4); + @param r The register to set. + @param value The value to set. If the register is only 8 bit, the value will be truncated. + */ + void set_value_of_register(Register r, uint16_t value); - assemble_fetch_decode_execute(fdcb_page_, 3); - assemble_fetch_decode_execute(ddcb_page_, 3); + /*! + Gets the value of the HALT output line. + */ + inline bool get_halt_line(); - MicroOp reset_program[] = Sequence(InternalOperation(6), {MicroOp::Reset}); + /*! + Sets the logical value of the interrupt line. - // Justification for NMI timing: per Wilf Rigter on the ZX81 (http://www.user.dccnet.com/wrigter/index_files/ZX81WAIT.htm), - // wait cycles occur between T2 and T3 during NMI; extending the refresh cycle is also consistent with my guess - // for the action of other non-four-cycle opcode fetches - MicroOp nmi_program[] = { - { MicroOp::BeginNMI }, - BusOp(ReadOpcodeStart()), - BusOp(ReadOpcodeWait(true)), - BusOp(ReadOpcodeEnd()), - BusOp(Refresh(6)), - Push(pc_), - { MicroOp::JumpTo66, nullptr, nullptr}, - { MicroOp::MoveToNextProgram } - }; - MicroOp irq_mode0_program[] = { - { MicroOp::BeginIRQMode0 }, - BusOp(IntAckStart(5, operation_)), - BusOp(IntWait(operation_)), - BusOp(IntAckEnd(operation_)), - { MicroOp::DecodeOperationNoRChange } - }; - MicroOp irq_mode1_program[] = { - { MicroOp::BeginIRQ }, - BusOp(IntAckStart(7, operation_)), // 7 half cycles (including + - BusOp(IntWait(operation_)), // [potentially 2 half cycles] + - BusOp(IntAckEnd(operation_)), // Implicitly 3 half cycles + - BusOp(Refresh(4)), // 4 half cycles + - Push(pc_), // 12 half cycles = 26 half cycles = 13 cycles - { MicroOp::Move16, &temp16_.full, &pc_.full }, - { MicroOp::MoveToNextProgram } - }; - MicroOp irq_mode2_program[] = { - { MicroOp::BeginIRQ }, - BusOp(IntAckStart(7, temp16_.bytes.low)), - BusOp(IntWait(temp16_.bytes.low)), - BusOp(IntAckEnd(temp16_.bytes.low)), - BusOp(Refresh(4)), - Push(pc_), - { MicroOp::Move8, &ir_.bytes.high, &temp16_.bytes.high }, - Read16(temp16_, pc_), - { MicroOp::MoveToNextProgram } - }; + @param offset If called while within perform_machine_cycle this may be a value indicating + how many cycles before now the line changed state. The value may not be longer than the + current machine cycle. If called at any other time, this must be zero. + */ + inline void set_interrupt_line(bool value, HalfCycles offset = 0); - copy_program(reset_program, reset_program_); - copy_program(nmi_program, nmi_program_); - copy_program(irq_mode0_program, irq_program_[0]); - copy_program(irq_mode1_program, irq_program_[1]); - copy_program(irq_mode2_program, irq_program_[2]); - } + /*! + Gets the value of the interrupt line. + */ + inline bool get_interrupt_line(); + + /*! + Sets the logical value of the non-maskable interrupt line. + + @param offset See discussion in set_interrupt_line. + */ + inline void set_non_maskable_interrupt_line(bool value, int offset = 0); + + /*! + Gets the value of the non-maskable interrupt line. + */ + inline bool get_non_maskable_interrupt_line(); + + /*! + Sets the logical value of the reset line. + */ + inline void set_reset_line(bool value); + + /*! + This emulation automatically sets itself up in power-on state at creation, which has the effect of triggering a + reset at the first opportunity. Use @c reset_power_on to disable that behaviour. + */ + void reset_power_on(); +}; + +/*! + @abstact Template providing emulation of a Z80 processor. + + @discussion Users should provide as the first template parameter a subclass of CPU::Z80::BusHandler; the Z80 + will announce its activity via the bus handler, which is responsible for marrying it to a bus. Users + can also nominate whether the processor includes support for the bus request and/or wait lines. Declining to + support either can produce a minor runtime performance improvement. +*/ +template class Processor: public ProcessorBase { + public: + Processor(T &bus_handler); /*! Runs the Z80 for a supplied number of cycles. @@ -915,1116 +246,37 @@ template class Processor { @param cycles The number of cycles to run for. */ - void run_for(const HalfCycles cycles) { - -#define advance_operation() \ - pc_increment_ = 1; \ - if(last_request_status_) { \ - halt_mask_ = 0xff; \ - if(last_request_status_ & (Interrupt::PowerOn | Interrupt::Reset)) { \ - request_status_ &= ~Interrupt::PowerOn; \ - scheduled_program_counter_ = reset_program_.data(); \ - } else if(last_request_status_ & Interrupt::NMI) { \ - request_status_ &= ~Interrupt::NMI; \ - scheduled_program_counter_ = nmi_program_.data(); \ - } else if(last_request_status_ & Interrupt::IRQ) { \ - scheduled_program_counter_ = irq_program_[interrupt_mode_].data(); \ - } \ - } else { \ - current_instruction_page_ = &base_page_; \ - scheduled_program_counter_ = base_page_.fetch_decode_execute_data; \ - } - - number_of_cycles_ += cycles; - if(!scheduled_program_counter_) { - advance_operation(); - } - - while(1) { - - do_bus_acknowledge: - while(uses_bus_request && bus_request_line_) { - static PartialMachineCycle bus_acknowledge_cycle = {PartialMachineCycle::BusAcknowledge, HalfCycles(2), nullptr, nullptr, false}; - number_of_cycles_ -= bus_handler_.perform_machine_cycle(bus_acknowledge_cycle) + HalfCycles(1); - if(!number_of_cycles_) { - bus_handler_.flush(); - return; - } - } - - while(true) { - const MicroOp *operation = scheduled_program_counter_; - scheduled_program_counter_++; - -#define set_parity(v) \ - parity_overflow_result_ = (uint8_t)(v^1);\ - parity_overflow_result_ ^= parity_overflow_result_ >> 4;\ - parity_overflow_result_ ^= parity_overflow_result_ << 2;\ - parity_overflow_result_ ^= parity_overflow_result_ >> 1; - - switch(operation->type) { - case MicroOp::BusOperation: - if(number_of_cycles_ < operation->machine_cycle.length) { - scheduled_program_counter_--; - bus_handler_.flush(); - return; - } - if(uses_wait_line && operation->machine_cycle.was_requested) { - if(wait_line_) { - scheduled_program_counter_--; - } else { - continue; - } - } - number_of_cycles_ -= operation->machine_cycle.length; - last_request_status_ = request_status_; - number_of_cycles_ -= bus_handler_.perform_machine_cycle(operation->machine_cycle); - if(uses_bus_request && bus_request_line_) goto do_bus_acknowledge; - break; - case MicroOp::MoveToNextProgram: - advance_operation(); - break; - case MicroOp::DecodeOperation: - refresh_addr_ = ir_; - ir_.bytes.low = (ir_.bytes.low & 0x80) | ((ir_.bytes.low + current_instruction_page_->r_step) & 0x7f); - pc_.full += pc_increment_ & (uint16_t)halt_mask_; - scheduled_program_counter_ = current_instruction_page_->instructions[operation_ & halt_mask_]; - break; - case MicroOp::DecodeOperationNoRChange: - refresh_addr_ = ir_; - pc_.full += pc_increment_ & (uint16_t)halt_mask_; - scheduled_program_counter_ = current_instruction_page_->instructions[operation_ & halt_mask_]; - break; - - case MicroOp::Increment16: (*(uint16_t *)operation->source)++; break; - case MicroOp::IncrementPC: pc_.full += pc_increment_; break; - case MicroOp::Decrement16: (*(uint16_t *)operation->source)--; break; - case MicroOp::Move8: *(uint8_t *)operation->destination = *(uint8_t *)operation->source; break; - case MicroOp::Move16: *(uint16_t *)operation->destination = *(uint16_t *)operation->source; break; - - case MicroOp::AssembleAF: - temp16_.bytes.high = a_; - temp16_.bytes.low = get_flags(); - break; - case MicroOp::DisassembleAF: - a_ = temp16_.bytes.high; - set_flags(temp16_.bytes.low); - break; - -#pragma mark - Logical - -#define set_logical_flags(hf) \ - sign_result_ = zero_result_ = bit53_result_ = a_; \ - set_parity(a_); \ - half_carry_result_ = hf; \ - subtract_flag_ = 0; \ - carry_result_ = 0; - - case MicroOp::And: - a_ &= *(uint8_t *)operation->source; - set_logical_flags(Flag::HalfCarry); - break; - - case MicroOp::Or: - a_ |= *(uint8_t *)operation->source; - set_logical_flags(0); - break; - - case MicroOp::Xor: - a_ ^= *(uint8_t *)operation->source; - set_logical_flags(0); - break; - -#undef set_logical_flags - - case MicroOp::CPL: - a_ ^= 0xff; - subtract_flag_ = Flag::Subtract; - half_carry_result_ = Flag::HalfCarry; - bit53_result_ = a_; - break; - - case MicroOp::CCF: - half_carry_result_ = (uint8_t)(carry_result_ << 4); - carry_result_ ^= Flag::Carry; - subtract_flag_ = 0; - bit53_result_ = a_; - break; - - case MicroOp::SCF: - carry_result_ = Flag::Carry; - half_carry_result_ = 0; - subtract_flag_ = 0; - bit53_result_ = a_; - break; - -#pragma mark - Flow control - - case MicroOp::DJNZ: - bc_.bytes.high--; - if(!bc_.bytes.high) { - advance_operation(); - } - break; - - case MicroOp::CalculateRSTDestination: - memptr_.full = operation_ & 0x38; - break; - -#pragma mark - 8-bit arithmetic - -#define set_arithmetic_flags(sub, b53) \ - sign_result_ = zero_result_ = (uint8_t)result; \ - carry_result_ = (uint8_t)(result >> 8); \ - half_carry_result_ = (uint8_t)half_result; \ - parity_overflow_result_ = (uint8_t)(overflow >> 5); \ - subtract_flag_ = sub; \ - bit53_result_ = (uint8_t)b53; - - case MicroOp::CP8: { - uint8_t value = *(uint8_t *)operation->source; - int result = a_ - value; - int half_result = (a_&0xf) - (value&0xf); - - // overflow for a subtraction is when the signs were originally - // different and the result is different again - int overflow = (value^a_) & (result^a_); - - // the 5 and 3 flags come from the operand, atypically - set_arithmetic_flags(Flag::Subtract, value); - } break; - - case MicroOp::SUB8: { - uint8_t value = *(uint8_t *)operation->source; - int result = a_ - value; - int half_result = (a_&0xf) - (value&0xf); - - // overflow for a subtraction is when the signs were originally - // different and the result is different again - int overflow = (value^a_) & (result^a_); - - a_ = (uint8_t)result; - set_arithmetic_flags(Flag::Subtract, result); - } break; - - case MicroOp::SBC8: { - uint8_t value = *(uint8_t *)operation->source; - int result = a_ - value - (carry_result_ & Flag::Carry); - int half_result = (a_&0xf) - (value&0xf) - (carry_result_ & Flag::Carry); - - // overflow for a subtraction is when the signs were originally - // different and the result is different again - int overflow = (value^a_) & (result^a_); - - a_ = (uint8_t)result; - set_arithmetic_flags(Flag::Subtract, result); - } break; - - case MicroOp::ADD8: { - uint8_t value = *(uint8_t *)operation->source; - int result = a_ + value; - int half_result = (a_&0xf) + (value&0xf); - - // overflow for addition is when the signs were originally - // the same and the result is different - int overflow = ~(value^a_) & (result^a_); - - a_ = (uint8_t)result; - set_arithmetic_flags(0, result); - } break; - - case MicroOp::ADC8: { - uint8_t value = *(uint8_t *)operation->source; - int result = a_ + value + (carry_result_ & Flag::Carry); - int half_result = (a_&0xf) + (value&0xf) + (carry_result_ & Flag::Carry); - - // overflow for addition is when the signs were originally - // the same and the result is different - int overflow = ~(value^a_) & (result^a_); - - a_ = (uint8_t)result; - set_arithmetic_flags(0, result); - } break; - -#undef set_arithmetic_flags - - case MicroOp::NEG: { - int overflow = (a_ == 0x80); - int result = -a_; - int halfResult = -(a_&0xf); - - a_ = (uint8_t)result; - bit53_result_ = sign_result_ = zero_result_ = a_; - parity_overflow_result_ = overflow ? Flag::Overflow : 0; - subtract_flag_ = Flag::Subtract; - carry_result_ = (uint8_t)(result >> 8); - half_carry_result_ = (uint8_t)halfResult; - } break; - - case MicroOp::Increment8: { - uint8_t value = *(uint8_t *)operation->source; - int result = value + 1; - - // with an increment, overflow occurs if the sign changes from - // positive to negative - int overflow = (value ^ result) & ~value; - int half_result = (value&0xf) + 1; - - *(uint8_t *)operation->source = (uint8_t)result; - - // sign, zero and 5 & 3 are set directly from the result - bit53_result_ = sign_result_ = zero_result_ = (uint8_t)result; - half_carry_result_ = (uint8_t)half_result; - parity_overflow_result_ = (uint8_t)(overflow >> 5); - subtract_flag_ = 0; - } break; - - case MicroOp::Decrement8: { - uint8_t value = *(uint8_t *)operation->source; - int result = value - 1; - - // with a decrement, overflow occurs if the sign changes from - // negative to positive - int overflow = (value ^ result) & value; - int half_result = (value&0xf) - 1; - - *(uint8_t *)operation->source = (uint8_t)result; - - // sign, zero and 5 & 3 are set directly from the result - bit53_result_ = sign_result_ = zero_result_ = (uint8_t)result; - half_carry_result_ = (uint8_t)half_result; - parity_overflow_result_ = (uint8_t)(overflow >> 5); - subtract_flag_ = Flag::Subtract; - } break; - - case MicroOp::DAA: { - int lowNibble = a_ & 0xf; - int highNibble = a_ >> 4; - int amountToAdd = 0; - - if(carry_result_ & Flag::Carry) - { - amountToAdd = (lowNibble > 0x9 || (half_carry_result_ & Flag::HalfCarry)) ? 0x66 : 0x60; - } - else - { - if(half_carry_result_ & Flag::HalfCarry) - { - if(lowNibble > 0x9) - amountToAdd = (highNibble > 0x8) ? 0x66 : 0x06; - else - amountToAdd = (highNibble > 0x9) ? 0x66 : 0x06; - } - else - { - if(lowNibble > 0x9) - amountToAdd = (highNibble > 0x8) ? 0x66 : 0x06; - else - amountToAdd = (highNibble > 0x9) ? 0x60 : 0x00; - } - } - - if(!(carry_result_ & Flag::Carry)) - { - if(lowNibble > 0x9) - { - if(highNibble > 0x8) carry_result_ = Flag::Carry; - } - else - { - if(highNibble > 0x9) carry_result_ = Flag::Carry; - } - } - - if(subtract_flag_) - { - a_ -= amountToAdd; - half_carry_result_ = ((half_carry_result_ & Flag::HalfCarry) && lowNibble < 0x6) ? Flag::HalfCarry : 0; - } - else - { - a_ += amountToAdd; - half_carry_result_ = (lowNibble > 0x9) ? Flag::HalfCarry : 0; - } - - sign_result_ = zero_result_ = bit53_result_ = a_; - - set_parity(a_); - } break; - -#pragma mark - 16-bit arithmetic - - case MicroOp::ADD16: { - memptr_.full = *(uint16_t *)operation->destination; - uint16_t sourceValue = *(uint16_t *)operation->source; - uint16_t destinationValue = memptr_.full; - int result = sourceValue + destinationValue; - int halfResult = (sourceValue&0xfff) + (destinationValue&0xfff); - - bit53_result_ = (uint8_t)(result >> 8); - carry_result_ = (uint8_t)(result >> 16); - half_carry_result_ = (uint8_t)(halfResult >> 8); - subtract_flag_ = 0; - - *(uint16_t *)operation->destination = (uint16_t)result; - memptr_.full++; - } break; - - case MicroOp::ADC16: { - memptr_.full = *(uint16_t *)operation->destination; - uint16_t sourceValue = *(uint16_t *)operation->source; - uint16_t destinationValue = memptr_.full; - int result = sourceValue + destinationValue + (carry_result_ & Flag::Carry); - int halfResult = (sourceValue&0xfff) + (destinationValue&0xfff) + (carry_result_ & Flag::Carry); - - int overflow = (result ^ destinationValue) & ~(destinationValue ^ sourceValue); - - bit53_result_ = - sign_result_ = (uint8_t)(result >> 8); - zero_result_ = (uint8_t)(result | sign_result_); - subtract_flag_ = 0; - carry_result_ = (uint8_t)(result >> 16); - half_carry_result_ = (uint8_t)(halfResult >> 8); - parity_overflow_result_ = (uint8_t)(overflow >> 13); - - *(uint16_t *)operation->destination = (uint16_t)result; - memptr_.full++; - } break; - - case MicroOp::SBC16: { - memptr_.full = *(uint16_t *)operation->destination; - uint16_t sourceValue = *(uint16_t *)operation->source; - uint16_t destinationValue = memptr_.full; - int result = destinationValue - sourceValue - (carry_result_ & Flag::Carry); - int halfResult = (destinationValue&0xfff) - (sourceValue&0xfff) - (carry_result_ & Flag::Carry); - - // subtraction, so parity rules are: - // signs of operands were different, - // sign of result is different - int overflow = (result ^ destinationValue) & (sourceValue ^ destinationValue); - - bit53_result_ = - sign_result_ = (uint8_t)(result >> 8); - zero_result_ = (uint8_t)(result | sign_result_); - subtract_flag_ = Flag::Subtract; - carry_result_ = (uint8_t)(result >> 16); - half_carry_result_ = (uint8_t)(halfResult >> 8); - parity_overflow_result_ = (uint8_t)(overflow >> 13); - - *(uint16_t *)operation->destination = (uint16_t)result; - memptr_.full++; - } break; - -#pragma mark - Conditionals - -#define decline_conditional() \ - if(operation->source) { \ - scheduled_program_counter_ = (MicroOp *)operation->source; \ - } else { \ - advance_operation(); \ - } - - case MicroOp::TestNZ: if(!zero_result_) { decline_conditional(); } break; - case MicroOp::TestZ: if(zero_result_) { decline_conditional(); } break; - case MicroOp::TestNC: if(carry_result_ & Flag::Carry) { decline_conditional(); } break; - case MicroOp::TestC: if(!(carry_result_ & Flag::Carry)) { decline_conditional(); } break; - case MicroOp::TestPO: if(parity_overflow_result_ & Flag::Parity) { decline_conditional(); } break; - case MicroOp::TestPE: if(!(parity_overflow_result_ & Flag::Parity)) { decline_conditional(); } break; - case MicroOp::TestP: if(sign_result_ & Flag::Sign) { decline_conditional(); } break; - case MicroOp::TestM: if(!(sign_result_ & Flag::Sign)) { decline_conditional(); } break; - -#undef decline_conditional - -#pragma mark - Exchange - -#define swap(a, b) temp = a.full; a.full = b.full; b.full = temp; - - case MicroOp::ExDEHL: { - uint16_t temp; - swap(de_, hl_); - } break; - - case MicroOp::ExAFAFDash: { - uint8_t a = a_; - uint8_t f = get_flags(); - set_flags(afDash_.bytes.low); - a_ = afDash_.bytes.high; - afDash_.bytes.high = a; - afDash_.bytes.low = f; - } break; - - case MicroOp::EXX: { - uint16_t temp; - swap(de_, deDash_); - swap(bc_, bcDash_); - swap(hl_, hlDash_); - } break; - -#undef swap - -#pragma mark - Repetition - -#define REPEAT(test) \ - if(test) { \ - pc_.full -= 2; \ - } else { \ - advance_operation(); \ - } - -#define LDxR_STEP(dir) \ - bc_.full--; \ - de_.full += dir; \ - hl_.full += dir; \ - uint8_t sum = a_ + temp8_; \ - bit53_result_ = (uint8_t)((sum&0x8) | ((sum & 0x02) << 4)); \ - subtract_flag_ = 0; \ - half_carry_result_ = 0; \ - parity_overflow_result_ = bc_.full ? Flag::Parity : 0; - - case MicroOp::LDDR: { - LDxR_STEP(-1); - REPEAT(bc_.full); - } break; - - case MicroOp::LDIR: { - LDxR_STEP(1); - REPEAT(bc_.full); - } break; - - case MicroOp::LDD: { - LDxR_STEP(-1); - } break; - - case MicroOp::LDI: { - LDxR_STEP(1); - } break; - -#undef LDxR_STEP - -#define CPxR_STEP(dir) \ - hl_.full += dir; \ - bc_.full--; \ - \ - uint8_t result = a_ - temp8_; \ - uint8_t halfResult = (a_&0xf) - (temp8_&0xf); \ - \ - parity_overflow_result_ = bc_.full ? Flag::Parity : 0; \ - half_carry_result_ = halfResult; \ - subtract_flag_ = Flag::Subtract; \ - sign_result_ = zero_result_ = result; \ - \ - result -= (halfResult >> 4)&1; \ - bit53_result_ = (uint8_t)((result&0x8) | ((result&0x2) << 4)); \ - - case MicroOp::CPDR: { - CPxR_STEP(-1); - REPEAT(bc_.full && sign_result_); - } break; - - case MicroOp::CPIR: { - CPxR_STEP(1); - REPEAT(bc_.full && sign_result_); - } break; - - case MicroOp::CPD: { - memptr_.full--; - CPxR_STEP(-1); - } break; - - case MicroOp::CPI: { - memptr_.full++; - CPxR_STEP(1); - } break; - -#undef CPxR_STEP - -#define INxR_STEP(dir) \ - bc_.bytes.high--; \ - hl_.full += dir; \ - \ - sign_result_ = zero_result_ = bit53_result_ = bc_.bytes.high; \ - subtract_flag_ = (temp8_ >> 6) & Flag::Subtract; \ - \ - int next_bc = bc_.bytes.low + dir; \ - int summation = temp8_ + (next_bc&0xff); \ - \ - if(summation > 0xff) { \ - carry_result_ = Flag::Carry; \ - half_carry_result_ = Flag::HalfCarry; \ - } else { \ - carry_result_ = 0; \ - half_carry_result_ = 0; \ - } \ - \ - summation = (summation&7) ^ bc_.bytes.high; \ - set_parity(summation); - - case MicroOp::INDR: { - INxR_STEP(-1); - REPEAT(bc_.bytes.high); - } break; - - case MicroOp::INIR: { - INxR_STEP(1); - REPEAT(bc_.bytes.high); - } break; - - case MicroOp::IND: { - memptr_.full = bc_.full - 1; - INxR_STEP(-1); - } break; - - case MicroOp::INI: { - memptr_.full = bc_.full + 1; - INxR_STEP(1); - } break; - -#undef INxR_STEP - -#define OUTxR_STEP(dir) \ - bc_.bytes.high--; \ - hl_.full += dir; \ - \ - sign_result_ = zero_result_ = bit53_result_ = bc_.bytes.high; \ - subtract_flag_ = (temp8_ >> 6) & Flag::Subtract; \ - \ - int summation = temp8_ + hl_.bytes.low; \ - if(summation > 0xff) { \ - carry_result_ = Flag::Carry; \ - half_carry_result_ = Flag::HalfCarry; \ - } else { \ - carry_result_ = half_carry_result_ = 0; \ - } \ - \ - summation = (summation&7) ^ bc_.bytes.high; \ - set_parity(summation); - - case MicroOp::OUT_R: - REPEAT(bc_.bytes.high); - break; - - case MicroOp::OUTD: { - OUTxR_STEP(-1); - memptr_.full = bc_.full - 1; - } break; - - case MicroOp::OUTI: { - OUTxR_STEP(1); - memptr_.full = bc_.full + 1; - } break; - -#undef OUTxR_STEP - -#pragma mark - Bit Manipulation - - case MicroOp::BIT: { - uint8_t result = *(uint8_t *)operation->source & (1 << ((operation_ >> 3)&7)); - - if(current_instruction_page_->is_indexed || ((operation_&0x08) == 7)) { - bit53_result_ = memptr_.bytes.high; - } else { - bit53_result_ = *(uint8_t *)operation->source; - } - - sign_result_ = zero_result_ = result; - half_carry_result_ = Flag::HalfCarry; - subtract_flag_ = 0; - parity_overflow_result_ = result ? 0 : Flag::Parity; - } break; - - case MicroOp::RES: - *(uint8_t *)operation->source &= ~(1 << ((operation_ >> 3)&7)); - break; - - case MicroOp::SET: - *(uint8_t *)operation->source |= (1 << ((operation_ >> 3)&7)); - break; - -#pragma mark - Rotation and shifting - -#define set_rotate_flags() \ - bit53_result_ = a_; \ - carry_result_ = new_carry; \ - subtract_flag_ = half_carry_result_ = 0; - - case MicroOp::RLA: { - uint8_t new_carry = a_ >> 7; - a_ = (uint8_t)((a_ << 1) | (carry_result_ & Flag::Carry)); - set_rotate_flags(); - } break; - - case MicroOp::RRA: { - uint8_t new_carry = a_ & 1; - a_ = (uint8_t)((a_ >> 1) | (carry_result_ << 7)); - set_rotate_flags(); - } break; - - case MicroOp::RLCA: { - uint8_t new_carry = a_ >> 7; - a_ = (uint8_t)((a_ << 1) | new_carry); - set_rotate_flags(); - } break; - - case MicroOp::RRCA: { - uint8_t new_carry = a_ & 1; - a_ = (uint8_t)((a_ >> 1) | (new_carry << 7)); - set_rotate_flags(); - } break; - -#undef set_rotate_flags - -#define set_shift_flags() \ - sign_result_ = zero_result_ = bit53_result_ = *(uint8_t *)operation->source; \ - set_parity(sign_result_); \ - half_carry_result_ = 0; \ - subtract_flag_ = 0; - - case MicroOp::RLC: - carry_result_ = *(uint8_t *)operation->source >> 7; - *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source << 1) | carry_result_); - set_shift_flags(); - break; - - case MicroOp::RRC: - carry_result_ = *(uint8_t *)operation->source; - *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source >> 1) | (carry_result_ << 7)); - set_shift_flags(); - break; - - case MicroOp::RL: { - uint8_t next_carry = *(uint8_t *)operation->source >> 7; - *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source << 1) | (carry_result_ & Flag::Carry)); - carry_result_ = next_carry; - set_shift_flags(); - } break; - - case MicroOp::RR: { - uint8_t next_carry = *(uint8_t *)operation->source; - *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source >> 1) | (carry_result_ << 7)); - carry_result_ = next_carry; - set_shift_flags(); - } break; - - case MicroOp::SLA: - carry_result_ = *(uint8_t *)operation->source >> 7; - *(uint8_t *)operation->source = (uint8_t)(*(uint8_t *)operation->source << 1); - set_shift_flags(); - break; - - case MicroOp::SRA: - carry_result_ = *(uint8_t *)operation->source; - *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source >> 1) | (*(uint8_t *)operation->source & 0x80)); - set_shift_flags(); - break; - - case MicroOp::SLL: - carry_result_ = *(uint8_t *)operation->source >> 7; - *(uint8_t *)operation->source = (uint8_t)(*(uint8_t *)operation->source << 1) | 1; - set_shift_flags(); - break; - - case MicroOp::SRL: - carry_result_ = *(uint8_t *)operation->source; - *(uint8_t *)operation->source = (uint8_t)((*(uint8_t *)operation->source >> 1)); - set_shift_flags(); - break; - -#undef set_shift_flags - -#define set_decimal_rotate_flags() \ - subtract_flag_ = 0; \ - half_carry_result_ = 0; \ - set_parity(a_); \ - bit53_result_ = zero_result_ = sign_result_ = a_; - - case MicroOp::RRD: { - memptr_.full = hl_.full + 1; - uint8_t low_nibble = a_ & 0xf; - a_ = (a_ & 0xf0) | (temp8_ & 0xf); - temp8_ = (uint8_t)((temp8_ >> 4) | (low_nibble << 4)); - set_decimal_rotate_flags(); - } break; - - case MicroOp::RLD: { - memptr_.full = hl_.full + 1; - uint8_t low_nibble = a_ & 0xf; - a_ = (a_ & 0xf0) | (temp8_ >> 4); - temp8_ = (uint8_t)((temp8_ << 4) | low_nibble); - set_decimal_rotate_flags(); - } break; - -#undef set_decimal_rotate_flags - - -#pragma mark - Interrupt state - - case MicroOp::EI: - iff1_ = iff2_ = true; - if(irq_line_) request_status_ |= Interrupt::IRQ; - break; - - case MicroOp::DI: - iff1_ = iff2_ = false; - request_status_ &= ~Interrupt::IRQ; - break; - - case MicroOp::IM: - switch(operation_ & 0x18) { - case 0x00: interrupt_mode_ = 0; break; - case 0x08: interrupt_mode_ = 0; break; // IM 0/1 - case 0x10: interrupt_mode_ = 1; break; - case 0x18: interrupt_mode_ = 2; break; - } - break; - -#pragma mark - Input - - case MicroOp::SetInFlags: - subtract_flag_ = half_carry_result_ = 0; - sign_result_ = zero_result_ = bit53_result_ = *(uint8_t *)operation->source; - set_parity(sign_result_); - break; - - case MicroOp::SetAFlags: - subtract_flag_ = half_carry_result_ = 0; - parity_overflow_result_ = iff2_ ? Flag::Parity : 0; - sign_result_ = zero_result_ = bit53_result_ = a_; - break; - - case MicroOp::SetZero: - temp8_ = 0; - break; - -#pragma mark - Special-case Flow - - case MicroOp::BeginIRQMode0: - pc_increment_ = 0; // deliberate fallthrough - case MicroOp::BeginIRQ: - iff2_ = iff1_ = false; - request_status_ &= ~Interrupt::IRQ; - temp16_.full = 0x38; - break; - - case MicroOp::BeginNMI: - iff2_ = iff1_; - iff1_ = false; - request_status_ &= ~Interrupt::IRQ; - break; - - case MicroOp::JumpTo66: - pc_.full = 0x66; - break; - - case MicroOp::RETN: - iff1_ = iff2_; - if(irq_line_ && iff1_) request_status_ |= Interrupt::IRQ; - break; - - case MicroOp::HALT: - halt_mask_ = 0x00; - break; - -#pragma mark - Interrupt handling - - case MicroOp::Reset: - iff1_ = iff2_ = false; - interrupt_mode_ = 0; - pc_.full = 0; - sp_.full = 0xffff; - a_ = 0xff; - set_flags(0xff); - ir_.full = 0; - break; - -#pragma mark - Internal bookkeeping - - case MicroOp::SetInstructionPage: - current_instruction_page_ = (InstructionPage *)operation->source; - scheduled_program_counter_ = current_instruction_page_->fetch_decode_execute_data; - break; - - case MicroOp::CalculateIndexAddress: - memptr_.full = (uint16_t)(*(uint16_t *)operation->source + (int8_t)temp8_); - break; - - case MicroOp::IndexedPlaceHolder: - printf("Hit placeholder!!!\n"); - return; - } -#undef set_parity - } - - } - } + void run_for(const HalfCycles cycles); /*! - Called to announce the end of a run_for period, allowing deferred work to take place. - - Users of the Z80 template may override this. + Sets the logical value of the bus request line, having asserted that this Z80 supports the bus request line. */ - void flush() {} - - HalfCycles perform_machine_cycle(const PartialMachineCycle &cycle) { - return HalfCycles(0); - } + void set_bus_request_line(bool value); /*! - Gets the flags register. - - @see set_flags - - @returns The current value of the flags register. + Gets the logical value of the bus request line. */ - uint8_t get_flags() { - uint8_t result = - (sign_result_ & Flag::Sign) | - (zero_result_ ? 0 : Flag::Zero) | - (bit53_result_ & (Flag::Bit5 | Flag::Bit3)) | - (half_carry_result_ & Flag::HalfCarry) | - (parity_overflow_result_ & Flag::Parity) | - subtract_flag_ | - (carry_result_ & Flag::Carry); - return result; - } + bool get_bus_request_line(); /*! - Sets the flags register. - - @see set_flags - - @param flags The new value of the flags register. + Sets the logical value of the wait line, having asserted that this Z80 supports the wait line. */ - void set_flags(uint8_t flags) { - sign_result_ = flags; - zero_result_ = (flags & Flag::Zero) ^ Flag::Zero; - bit53_result_ = flags; - half_carry_result_ = flags; - parity_overflow_result_ = flags; - subtract_flag_ = flags & Flag::Subtract; - carry_result_ = flags; - } + void set_wait_line(bool value); /*! - Gets the value of a register. - - @see set_value_of_register - - @param r The register to set. - @returns The value of the register. 8-bit registers will be returned as unsigned. + Gets the logical value of the bus request line. */ - uint16_t get_value_of_register(Register r) { - switch (r) { - case Register::ProgramCounter: return pc_.full; - case Register::StackPointer: return sp_.full; + bool get_wait_line(); - case Register::A: return a_; - case Register::Flags: return get_flags(); - case Register::AF: return (uint16_t)((a_ << 8) | get_flags()); - case Register::B: return bc_.bytes.high; - case Register::C: return bc_.bytes.low; - case Register::BC: return bc_.full; - case Register::D: return de_.bytes.high; - case Register::E: return de_.bytes.low; - case Register::DE: return de_.full; - case Register::H: return hl_.bytes.high; - case Register::L: return hl_.bytes.low; - case Register::HL: return hl_.full; + private: + T &bus_handler_; - case Register::ADash: return afDash_.bytes.high; - case Register::FlagsDash: return afDash_.bytes.low; - case Register::AFDash: return afDash_.full; - case Register::BDash: return bcDash_.bytes.high; - case Register::CDash: return bcDash_.bytes.low; - case Register::BCDash: return bcDash_.full; - case Register::DDash: return deDash_.bytes.high; - case Register::EDash: return deDash_.bytes.low; - case Register::DEDash: return deDash_.full; - case Register::HDash: return hlDash_.bytes.high; - case Register::LDash: return hlDash_.bytes.low; - case Register::HLDash: return hlDash_.full; - - case Register::IXh: return ix_.bytes.high; - case Register::IXl: return ix_.bytes.low; - case Register::IX: return ix_.full; - case Register::IYh: return iy_.bytes.high; - case Register::IYl: return iy_.bytes.low; - case Register::IY: return iy_.full; - - case Register::R: return ir_.bytes.low; - case Register::I: return ir_.bytes.high; - case Register::Refresh: return ir_.full; - - case Register::IFF1: return iff1_ ? 1 : 0; - case Register::IFF2: return iff2_ ? 1 : 0; - case Register::IM: return (uint16_t)interrupt_mode_; - - case Register::MemPtr: return memptr_.full; - - default: return 0; - } - } - - /*! - Sets the value of a register. - - @see get_value_of_register - - @param r The register to set. - @param value The value to set. If the register is only 8 bit, the value will be truncated. - */ - void set_value_of_register(Register r, uint16_t value) { - switch (r) { - case Register::ProgramCounter: pc_.full = value; break; - case Register::StackPointer: sp_.full = value; break; - - case Register::A: a_ = (uint8_t)value; break; - case Register::AF: a_ = (uint8_t)(value >> 8); // deliberate fallthrough... - case Register::Flags: set_flags((uint8_t)value); break; - - case Register::B: bc_.bytes.high = (uint8_t)value; break; - case Register::C: bc_.bytes.low = (uint8_t)value; break; - case Register::BC: bc_.full = value; break; - case Register::D: de_.bytes.high = (uint8_t)value; break; - case Register::E: de_.bytes.low = (uint8_t)value; break; - case Register::DE: de_.full = value; break; - case Register::H: hl_.bytes.high = (uint8_t)value; break; - case Register::L: hl_.bytes.low = (uint8_t)value; break; - case Register::HL: hl_.full = value; break; - - case Register::ADash: afDash_.bytes.high = (uint8_t)value; break; - case Register::FlagsDash: afDash_.bytes.low = (uint8_t)value; break; - case Register::AFDash: afDash_.full = value; break; - case Register::BDash: bcDash_.bytes.high = (uint8_t)value; break; - case Register::CDash: bcDash_.bytes.low = (uint8_t)value; break; - case Register::BCDash: bcDash_.full = value; break; - case Register::DDash: deDash_.bytes.high = (uint8_t)value; break; - case Register::EDash: deDash_.bytes.low = (uint8_t)value; break; - case Register::DEDash: deDash_.full = value; break; - case Register::HDash: hlDash_.bytes.high = (uint8_t)value; break; - case Register::LDash: hlDash_.bytes.low = (uint8_t)value; break; - case Register::HLDash: hlDash_.full = value; break; - - case Register::IXh: ix_.bytes.high = (uint8_t)value; break; - case Register::IXl: ix_.bytes.low = (uint8_t)value; break; - case Register::IX: ix_.full = value; break; - case Register::IYh: iy_.bytes.high = (uint8_t)value; break; - case Register::IYl: iy_.bytes.low = (uint8_t)value; break; - case Register::IY: iy_.full = value; break; - - case Register::R: ir_.bytes.low = (uint8_t)value; break; - case Register::I: ir_.bytes.high = (uint8_t)value; break; - case Register::Refresh: ir_.full = (uint16_t)value; break; - - case Register::IFF1: iff1_ = !!value; break; - case Register::IFF2: iff2_ = !!value; break; - case Register::IM: interrupt_mode_ = value % 3; break; - - case Register::MemPtr: memptr_.full = value; break; - - default: break; - } - } - - /*! - Gets the value of the HALT output line. - */ - bool get_halt_line() { - return halt_mask_ == 0x00; - } - - /*! - Sets the logical value of the interrupt line. - - @param offset If called while within perform_machine_cycle this may be a value indicating - how many cycles before now the line changed state. The value may not be longer than the - current machine cycle. If called at any other time, this must be zero. - */ - void set_interrupt_line(bool value, HalfCycles offset = 0) { - if(irq_line_ == value) return; - - // IRQ requests are level triggered and masked. - irq_line_ = value; - if(irq_line_ && iff1_) { - request_status_ |= Interrupt::IRQ; - } else { - request_status_ &= ~Interrupt::IRQ; - } - - // If this change happened at least one cycle ago then: (i) we're promised that this is a machine - // cycle per the contract on supplying an offset; and (ii) that means it happened before the lines - // were sampled. So adjust the most recent sample. - if(offset <= HalfCycles(-2)) { - last_request_status_ = (last_request_status_ & ~Interrupt::IRQ) | (request_status_ & Interrupt::IRQ); - } - } - - bool get_interrupt_line() { - return irq_line_; - } - - /*! - Sets the logical value of the non-maskable interrupt line. - - @param offset See discussion in set_interrupt_line. - */ - void set_non_maskable_interrupt_line(bool value, int offset = 0) { - // NMIs are edge triggered and cannot be masked. - nmi_line_ = value; - if(value) { - request_status_ |= Interrupt::NMI; - if(offset < 0) { - last_request_status_ |= Interrupt::NMI; - } - } - } - - bool get_non_maskable_interrupt_line() { - return nmi_line_; - } - - /*! - Sets the logical value of the bus request line. - */ - void set_bus_request_line(bool value) { - assert(uses_bus_request); - bus_request_line_ = value; - } - - bool get_bus_request_line() { - return bus_request_line_; - } - - /*! - Sets the logical value of the reset line. - */ - void set_reset_line(bool value) { - // Reset requests are level triggered and cannot be masked. - if(value) request_status_ |= Interrupt::Reset; - else request_status_ &= ~Interrupt::Reset; - } - - /*! - This emulation automatically sets itself up in power-on state at creation, which has the effect of triggering a - reset at the first opportunity. Use @c reset_power_on to disable that behaviour. - */ - inline void reset_power_on() { - request_status_ &= ~Interrupt::PowerOn; - last_request_status_ &= ~Interrupt::PowerOn; - } - - /*! - Sets the logical value of the wait line. - */ - inline void set_wait_line(bool value) { - assert(uses_wait_line); - wait_line_ = value; - } - - bool get_wait_line() { - return wait_line_; - } + void assemble_page(InstructionPage &target, InstructionTable &table, bool add_offsets); + void copy_program(const MicroOp *source, std::vector &destination); }; +#include "Implementation/Z80Implementation.hpp" + } } From e6ac939ae049cad9c3c4d9300c74c8c78744569e Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Fri, 1 Sep 2017 20:51:31 -0400 Subject: [PATCH 3/3] Reintroduces missing noexcept specifier. --- Processors/Z80/Implementation/Z80Base.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Processors/Z80/Implementation/Z80Base.cpp b/Processors/Z80/Implementation/Z80Base.cpp index dd78f3f3e..294fd6ef3 100644 --- a/Processors/Z80/Implementation/Z80Base.cpp +++ b/Processors/Z80/Implementation/Z80Base.cpp @@ -211,7 +211,7 @@ void ProcessorBase::set_value_of_register(Register r, uint16_t value) { } } -PartialMachineCycle::PartialMachineCycle(const PartialMachineCycle &rhs) : +PartialMachineCycle::PartialMachineCycle(const PartialMachineCycle &rhs) noexcept : operation(rhs.operation), length(rhs.length), address(rhs.address),