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https://github.com/TomHarte/CLK.git
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Adds absolute long, x.
Factors out the commonality of a closing read/write while I'm here.
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@ -120,24 +120,29 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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3) the data address is undefined.
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3) the data address is undefined.
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*/
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*/
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// 1a. Absolute a.
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// Performs the closing 8- or 16-bit read or write common to many modes below.
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static void absolute(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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static void read_write(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsolute); // Calculate data address.
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if(type == AccessType::Write) {
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if(type == AccessType::Write) {
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target(OperationPerform); // Perform operation to fill the data buffer.
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target(OperationPerform); // Perform operation to fill the data buffer.
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if(!is8bit) target(CycleStoreIncrementData); // Data low.
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if(!is8bit) target(CycleStoreIncrementData); // Data low.
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target(CycleStoreData); // Data [high].
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target(CycleStoreData); // Data [high].
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} else {
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} else {
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if(!is8bit) target(CycleFetchIncrementData); // Data low.
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if(!is8bit) target(CycleFetchIncrementData); // Data low.
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target(CycleFetchIncrementData); // Data [high].
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target(CycleFetchData); // Data [high].
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target(OperationPerform); // Perform operation from the data buffer.
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target(OperationPerform); // Perform operation from the data buffer.
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}
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}
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}
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// 1a. Absolute; a.
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static void absolute(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsolute); // Calculate data address.
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read_write(type, is8bit, target);
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};
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};
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// 1b. Absolute a, JMP.
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// 1b. Absolute; a, JMP.
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static void absolute_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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static void absolute_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // New PCL.
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target(CycleFetchIncrementPC); // New PCL.
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target(CycleFetchPC); // New PCH.
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target(CycleFetchPC); // New PCH.
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@ -145,7 +150,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(OperationPerform); // [JMP]
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target(OperationPerform); // [JMP]
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};
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};
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// 1c. Absolute a, JSR.
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// 1c. Absolute; a, JSR.
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static void absolute_jsr(AccessType, bool, const std::function<void(MicroOp)> &target) {
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static void absolute_jsr(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // New PCL.
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target(CycleFetchIncrementPC); // New PCL.
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target(CycleFetchPC); // New PCH.
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target(CycleFetchPC); // New PCH.
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@ -156,7 +161,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CyclePush); // PCL
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target(CyclePush); // PCL
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};
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};
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// 1d. Absolute read-modify-write.
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// 1d. Absolute; a, read-modify-write.
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static void absolute_rmw(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
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static void absolute_rmw(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(CycleFetchIncrementPC); // AAH.
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@ -174,7 +179,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CycleStoreData); // Data [low].
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target(CycleStoreData); // Data [low].
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};
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};
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// 2a. Absolute Indexed Indirect (a, x), JMP.
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// 2a. Absolute Indexed Indirect; (a, x), JMP.
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static void absolute_indexed_indirect_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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static void absolute_indexed_indirect_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchPC); // AAH.
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target(CycleFetchPC); // AAH.
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@ -185,7 +190,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(OperationPerform); // [JMP]
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target(OperationPerform); // [JMP]
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};
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};
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// 2b. Absolute Indexed Indirect (a, x), JSR.
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// 2b. Absolute Indexed Indirect; (a, x), JSR.
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static void absolute_indexed_indirect_jsr(AccessType, bool, const std::function<void(MicroOp)> &target) {
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static void absolute_indexed_indirect_jsr(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAL.
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@ -202,7 +207,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(OperationPerform); // ['JSR' (actually: JMP will do)]
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target(OperationPerform); // ['JSR' (actually: JMP will do)]
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}
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}
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// 3a. Absolute Indirect (a), JML.
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// 3a. Absolute Indirect; (a), JML.
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static void absolute_indirect_jml(AccessType, bool, const std::function<void(MicroOp)> &target) {
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static void absolute_indirect_jml(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // New AAL.
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target(CycleFetchIncrementPC); // New AAL.
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target(CycleFetchPC); // New AAH.
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target(CycleFetchPC); // New AAH.
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@ -215,7 +220,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(OperationPerform); // [JML]
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target(OperationPerform); // [JML]
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};
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};
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// 3b. Absolute Indirect (a), JMP.
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// 3b. Absolute Indirect; (a), JMP.
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static void absolute_indirect_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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static void absolute_indirect_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // New AAL.
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target(CycleFetchIncrementPC); // New AAL.
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target(CycleFetchPC); // New AAH.
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target(CycleFetchPC); // New AAH.
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@ -227,7 +232,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(OperationPerform); // [JMP]
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target(OperationPerform); // [JMP]
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};
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};
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// 4a. Absolute long al.
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// 4a. Absolute long; al.
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static void absolute_long(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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static void absolute_long(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(CycleFetchIncrementPC); // AAH.
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@ -235,18 +240,10 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(OperationConstructAbsolute); // Calculate data address.
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target(OperationConstructAbsolute); // Calculate data address.
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if(type == AccessType::Write) {
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read_write(type, is8bit, target);
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target(OperationPerform); // Perform operation to fill the data buffer.
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if(!is8bit) target(CycleStoreIncrementData); // Data low.
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target(CycleStoreData); // Data [high].
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} else {
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if(!is8bit) target(CycleFetchIncrementData); // Data low.
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target(CycleFetchData); // Data [high].
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target(OperationPerform); // Perform operation from the data buffer.
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}
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};
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};
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// 4b. Absolute long al, JMP.
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// 4b. Absolute long; al, JMP.
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static void absolute_long_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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static void absolute_long_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // New PCL.
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target(CycleFetchIncrementPC); // New PCL.
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target(CycleFetchIncrementPC); // New PCH.
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target(CycleFetchIncrementPC); // New PCH.
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@ -273,8 +270,20 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CyclePush); // PCH
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target(CyclePush); // PCH
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target(CyclePush); // PCL
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target(CyclePush); // PCL
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};
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};
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// 5. Absolute long, X; al, x.
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static void absolute_long_x(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(CycleFetchIncrementPC); // AAB.
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target(OperationConstructAbsoluteLongX); // Calculate data address.
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read_write(type, is8bit, target);
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}
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};
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};
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// TEMPORARY. Kneejerk way to get a step debug of 65816 storage construction.
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ProcessorStorage TEMPORARY_test_instance;
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ProcessorStorage TEMPORARY_test_instance;
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ProcessorStorage::ProcessorStorage() {
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ProcessorStorage::ProcessorStorage() {
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@ -315,7 +324,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x1c TRB a */
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/* 0x1c TRB a */
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/* 0x1d ORA a, x */
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/* 0x1d ORA a, x */
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/* 0x1e ASL a, x */
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/* 0x1e ASL a, x */
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/* 0x1f ORA al, x */
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/* 0x1f ORA al, x */ op(absolute_long_x, ORA);
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/* 0x20 JSR a */ op(absolute_jsr, JSR);
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/* 0x20 JSR a */ op(absolute_jsr, JSR);
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/* 0x21 ORA (d), y */
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/* 0x21 ORA (d), y */
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@ -349,7 +358,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x3c BIT a, x */
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/* 0x3c BIT a, x */
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/* 0x3d AND a, x */
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/* 0x3d AND a, x */
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/* 0x3e TLD a, x */
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/* 0x3e TLD a, x */
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/* 0x3f AND al, x */
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/* 0x3f AND al, x */ op(absolute_long_x, AND);
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/* 0x40 RTI s */
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/* 0x40 RTI s */
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/* 0x41 EOR (d, x) */
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/* 0x41 EOR (d, x) */
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@ -383,7 +392,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x5c JMP al */ op(absolute_long_jmp, JML); // [sic]; this updates PBR so it's JML.
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/* 0x5c JMP al */ op(absolute_long_jmp, JML); // [sic]; this updates PBR so it's JML.
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/* 0x5d EOR a, x */
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/* 0x5d EOR a, x */
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/* 0x5e LSR a, x */
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/* 0x5e LSR a, x */
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/* 0x5f EOR al, x */
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/* 0x5f EOR al, x */ op(absolute_long_x, EOR);
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/* 0x60 RTS s */
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/* 0x60 RTS s */
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/* 0x61 ADC (d, x) */
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/* 0x61 ADC (d, x) */
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@ -417,7 +426,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x7c JMP (a, x) */ op(absolute_indexed_indirect_jmp, JMP);
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/* 0x7c JMP (a, x) */ op(absolute_indexed_indirect_jmp, JMP);
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/* 0x7d ADC a, x */
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/* 0x7d ADC a, x */
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/* 0x7e ROR a, x */
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/* 0x7e ROR a, x */
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/* 0x7f ADC al, x */
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/* 0x7f ADC al, x */ op(absolute_long_x, ADC);
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/* 0x80 BRA r */
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/* 0x80 BRA r */
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/* 0x81 STA (d, x) */
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/* 0x81 STA (d, x) */
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@ -451,7 +460,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x9c STZ a */ op(absolute, STZ);
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/* 0x9c STZ a */ op(absolute, STZ);
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/* 0x9d STA a, x */
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/* 0x9d STA a, x */
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/* 0x9e STZ a, x */
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/* 0x9e STZ a, x */
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/* 0x9f STA al, x */
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/* 0x9f STA al, x */ op(absolute_long_x, STA);
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/* 0xa0 LDY # */
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/* 0xa0 LDY # */
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/* 0xa1 LDA (d, x) */
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/* 0xa1 LDA (d, x) */
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@ -485,7 +494,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xbc LDY a, x */
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/* 0xbc LDY a, x */
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/* 0xbd LDA a, x */
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/* 0xbd LDA a, x */
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/* 0xbe LDX a, y */
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/* 0xbe LDX a, y */
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/* 0xbf LDA al, x */
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/* 0xbf LDA al, x */ op(absolute_long_x, LDA);
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/* 0xc0 CPY # */
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/* 0xc0 CPY # */
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/* 0xc1 CMP (d, x) */
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/* 0xc1 CMP (d, x) */
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@ -519,7 +528,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xdc JML (a) */ op(absolute_indirect_jml, JML);
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/* 0xdc JML (a) */ op(absolute_indirect_jml, JML);
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/* 0xdd CMP a, x */
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/* 0xdd CMP a, x */
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/* 0xde DEC a, x */
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/* 0xde DEC a, x */
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/* 0xdf CMP al, x */
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/* 0xdf CMP al, x */ op(absolute_long_x, CMP);
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/* 0xe0 CPX # */
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/* 0xe0 CPX # */
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/* 0xe1 SBC (d, x) */
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/* 0xe1 SBC (d, x) */
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@ -553,7 +562,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xfc JSR (a, x) */ op(absolute_indexed_indirect_jsr, JMP); // [sic]
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/* 0xfc JSR (a, x) */ op(absolute_indexed_indirect_jsr, JMP); // [sic]
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/* 0xfd SBC a, x */
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/* 0xfd SBC a, x */
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/* 0xfe INC a, x */
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/* 0xfe INC a, x */
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/* 0xff SBC al, x */
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/* 0xff SBC al, x */ op(absolute_long_x, SBC);
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#undef op
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#undef op
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@ -37,6 +37,7 @@ enum MicroOp: uint8_t {
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/// Sets the data address to the result of (a, x).
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/// Sets the data address to the result of (a, x).
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/// TODO: explain better once implemented.
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/// TODO: explain better once implemented.
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OperationConstructAbsoluteIndexedIndirect,
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OperationConstructAbsoluteIndexedIndirect,
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OperationConstructAbsoluteLongX,
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/// Performs whatever operation goes with this program.
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/// Performs whatever operation goes with this program.
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OperationPerform,
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OperationPerform,
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