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Expands Disk DMA access window.
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aeaea073c6
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@ -273,7 +273,7 @@ template <int cycle, bool stop_if_cpu> bool Chipset::perform_cycle() {
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// 2. Refresh, disk, audio, or sprites. Depending on region.
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//
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// Blitter and CPU priority is dealt with below.
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if constexpr (cycle >= 4 && cycle <= 6) {
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if constexpr (cycle >= 7 && cycle < 13) {
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if((dma_control_ & DiskFlag) == DiskFlag) {
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if(disk_.advance()) {
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return false;
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@ -908,8 +908,12 @@ void Chipset::DiskDMA::enqueue(uint16_t value, bool matches_sync) {
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// TODO: handle matches_sync.
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(void)matches_sync;
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// LOG("In: " << buffer_write_);
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buffer_[buffer_write_ & 3] = value;
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if(buffer_write_ == buffer_read_ + 4) ++buffer_read_;
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if(buffer_write_ == buffer_read_ + 4) {
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++buffer_read_;
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}
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++buffer_write_;
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}
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@ -930,7 +934,9 @@ bool Chipset::DiskDMA::advance() {
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if(!write_) {
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// TODO: run an actual PLL, collect actual disk data.
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if(length_ && buffer_read_ != buffer_write_) {
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printf("Deposited %04x\n", buffer_[buffer_read_ & 3]);
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// LOG("Out: " << buffer_read_);
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printf("%04x\n", buffer_[buffer_read_ & 3]);
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ram_[pointer_[0] & ram_mask_] = buffer_[buffer_read_ & 3];
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++pointer_[0];
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--length_;
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@ -1107,6 +1113,7 @@ void Chipset::DiskController::process_index_hole() {
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// Resync word output. Experimental!!
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bit_count_ = 0;
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printf("IH\n");
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}
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void Chipset::DiskController::set_mtr_sel_side_dir_step(uint8_t value) {
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