mirror of
https://github.com/TomHarte/CLK.git
synced 2025-01-11 08:30:55 +00:00
Clean up Instruction.hpp.
This commit is contained in:
Thomas Harte
parent
539932dc56
commit
8e5650fde9
@ -18,6 +18,8 @@
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namespace InstructionSet {
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namespace M68k {
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/// Maps the 68k function codes such that bits 0, 1 and 2 represent
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/// FC0, FC1 and FC2 respectively.
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enum class FunctionCode {
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UserData = 0b001,
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UserProgram = 0b010,
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@ -44,7 +46,6 @@ template <Model model, typename BusHandler> class Executor {
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/// will not necessarily take effect immediately when signalled.
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void run_for_instructions(int);
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// Flow control.
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void consume_cycles(int) {}
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void set_pc(uint32_t);
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145
InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp
Normal file
145
InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp
Normal file
@ -0,0 +1,145 @@
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//
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// InstructionOperandFlags.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 09/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_68k_InstructionOperandFlags_hpp
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#define InstructionSets_68k_InstructionOperandFlags_hpp
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namespace InstructionSet {
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namespace M68k {
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template <Model model, Operation t_operation> uint8_t operand_flags(Operation r_operation) {
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switch((t_operation != Operation::Undefined) ? t_operation : r_operation) {
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default:
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assert(false);
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//
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// No operands are fetched or stored.
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// (which means that source and destination will appear as their effective addresses)
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//
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case Operation::PEA:
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case Operation::JMP: case Operation::JSR:
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case Operation::MOVEPw: case Operation::MOVEPl:
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case Operation::MOVEMtoMw: case Operation::MOVEMtoMl:
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case Operation::MOVEMtoRw: case Operation::MOVEMtoRl:
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case Operation::TAS:
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case Operation::RTR: case Operation::RTS: case Operation::RTE:
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return 0;
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//
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// Single-operand read.
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//
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case Operation::MOVEtoSR: case Operation::MOVEtoCCR: case Operation::MOVEtoUSP:
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case Operation::ORItoSR: case Operation::ORItoCCR:
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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case Operation::EORItoSR: case Operation::EORItoCCR:
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case Operation::Bccb: case Operation::Bccw: case Operation::Bccl:
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case Operation::BSRb: case Operation::BSRw: case Operation::BSRl:
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case Operation::TSTb: case Operation::TSTw: case Operation::TSTl:
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return FetchOp1;
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//
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// Single-operand write.
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//
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case Operation::MOVEfromSR: case Operation::MOVEfromUSP:
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case Operation::Scc:
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return StoreOp1;
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//
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// Single-operand read-modify-write.
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//
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case Operation::NBCD:
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case Operation::NOTb: case Operation::NOTw: case Operation::NOTl:
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case Operation::NEGb: case Operation::NEGw: case Operation::NEGl:
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case Operation::NEGXb: case Operation::NEGXw: case Operation::NEGXl:
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case Operation::EXTbtow: case Operation::EXTwtol:
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case Operation::SWAP:
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case Operation::UNLINK:
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case Operation::ASLm: case Operation::ASRm:
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case Operation::LSLm: case Operation::LSRm:
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case Operation::ROLm: case Operation::RORm:
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case Operation::ROXLm: case Operation::ROXRm:
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return FetchOp1 | StoreOp1;
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//
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// CLR, which is model-dependent.
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//
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case Operation::CLRb: case Operation::CLRw: case Operation::CLRl:
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if constexpr (model == Model::M68000) {
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return FetchOp1 | StoreOp1;
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} else {
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return StoreOp1;
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}
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//
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// Two-operand; read both.
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//
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case Operation::CMPb: case Operation::CMPw: case Operation::CMPl:
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case Operation::CMPAw: case Operation::CMPAl:
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case Operation::CHK:
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case Operation::BTST:
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case Operation::LINKw:
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return FetchOp1 | FetchOp2;
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//
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// Two-operand; read source, write dest.
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//
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case Operation::MOVEb: case Operation::MOVEw: case Operation::MOVEl:
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case Operation::MOVEAw: case Operation::MOVEAl:
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return FetchOp1 | StoreOp2;
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//
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// Two-operand; read both, write dest.
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//
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case Operation::ABCD: case Operation::SBCD:
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case Operation::ADDb: case Operation::ADDw: case Operation::ADDl:
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case Operation::ADDAw: case Operation::ADDAl:
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case Operation::ADDXb: case Operation::ADDXw: case Operation::ADDXl:
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case Operation::SUBb: case Operation::SUBw: case Operation::SUBl:
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case Operation::SUBAw: case Operation::SUBAl:
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case Operation::SUBXb: case Operation::SUBXw: case Operation::SUBXl:
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case Operation::ORb: case Operation::ORw: case Operation::ORl:
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case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
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case Operation::EORb: case Operation::EORw: case Operation::EORl:
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case Operation::DIVU: case Operation::DIVS:
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case Operation::MULU: case Operation::MULS:
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case Operation::ASLb: case Operation::ASLw: case Operation::ASLl:
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case Operation::ASRb: case Operation::ASRw: case Operation::ASRl:
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case Operation::LSLb: case Operation::LSLw: case Operation::LSLl:
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case Operation::LSRb: case Operation::LSRw: case Operation::LSRl:
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case Operation::ROLb: case Operation::ROLw: case Operation::ROLl:
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case Operation::RORb: case Operation::RORw: case Operation::RORl:
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case Operation::ROXLb: case Operation::ROXLw: case Operation::ROXLl:
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case Operation::ROXRb: case Operation::ROXRw: case Operation::ROXRl:
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case Operation::BCHG:
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case Operation::BCLR: case Operation::BSET:
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return FetchOp1 | FetchOp2 | StoreOp2;
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//
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// Two-operand; read both, write source.
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//
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case Operation::DBcc:
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return FetchOp1 | FetchOp2 | StoreOp1;
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//
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// Two-operand; read both, write both.
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//
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case Operation::EXG:
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return FetchOp1 | FetchOp2 | StoreOp1 | StoreOp2;
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//
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// Two-operand; just write destination.
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//
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case Operation::LEA:
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return StoreOp2;
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}
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}
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}
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}
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#endif /* InstructionSets_68k_InstructionOperandFlags_hpp */
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120
InstructionSets/M68k/Implementation/InstructionOperandSize.hpp
Normal file
120
InstructionSets/M68k/Implementation/InstructionOperandSize.hpp
Normal file
@ -0,0 +1,120 @@
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//
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// InstructionOperandSize.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 09/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_68k_InstructionOperandSize_hpp
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#define InstructionSets_68k_InstructionOperandSize_hpp
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namespace InstructionSet {
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namespace M68k {
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constexpr DataSize operand_size(Operation operation) {
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switch(operation) {
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// These are given a value arbitrarily, to
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// complete the switch statement.
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case Operation::Undefined:
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case Operation::NOP:
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case Operation::STOP:
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case Operation::RESET:
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case Operation::RTE: case Operation::RTR:
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case Operation::TRAP:
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case Operation::TRAPV:
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case Operation::ABCD: case Operation::SBCD:
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case Operation::NBCD:
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case Operation::ADDb: case Operation::ADDXb:
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case Operation::SUBb: case Operation::SUBXb:
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case Operation::MOVEb:
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case Operation::ORItoCCR:
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case Operation::ANDItoCCR:
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case Operation::EORItoCCR:
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case Operation::BTST: case Operation::BCLR:
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case Operation::BCHG: case Operation::BSET:
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case Operation::CMPb: case Operation::TSTb:
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case Operation::Bccb: case Operation::BSRb:
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case Operation::CLRb:
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case Operation::Scc:
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case Operation::NEGXb: case Operation::NEGb:
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case Operation::ASLb: case Operation::ASRb:
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case Operation::LSLb: case Operation::LSRb:
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case Operation::ROLb: case Operation::RORb:
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case Operation::ROXLb: case Operation::ROXRb:
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case Operation::ANDb: case Operation::EORb:
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case Operation::NOTb: case Operation::ORb:
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case Operation::TAS:
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return DataSize::Byte;
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case Operation::ADDw: case Operation::ADDAw:
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case Operation::ADDXw: case Operation::SUBw:
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case Operation::SUBAw: case Operation::SUBXw:
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case Operation::MOVEw: case Operation::MOVEAw:
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case Operation::ORItoSR:
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case Operation::ANDItoSR:
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case Operation::EORItoSR:
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case Operation::MOVEtoSR:
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case Operation::MOVEfromSR:
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case Operation::MOVEtoCCR:
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case Operation::CMPw: case Operation::CMPAw:
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case Operation::TSTw:
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case Operation::DBcc:
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case Operation::Bccw: case Operation::BSRw:
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case Operation::CLRw:
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case Operation::NEGXw: case Operation::NEGw:
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case Operation::ASLw: case Operation::ASLm:
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case Operation::ASRw: case Operation::ASRm:
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case Operation::LSLw: case Operation::LSLm:
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case Operation::LSRw: case Operation::LSRm:
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case Operation::ROLw: case Operation::ROLm:
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case Operation::RORw: case Operation::RORm:
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case Operation::ROXLw: case Operation::ROXLm:
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case Operation::ROXRw: case Operation::ROXRm:
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case Operation::MOVEMtoRw:
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case Operation::MOVEMtoRl:
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case Operation::MOVEMtoMw:
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case Operation::MOVEMtoMl:
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case Operation::MOVEPw:
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case Operation::ANDw: case Operation::EORw:
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case Operation::NOTw: case Operation::ORw:
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case Operation::DIVU: case Operation::DIVS:
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case Operation::MULU: case Operation::MULS:
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case Operation::EXTbtow:
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case Operation::LINKw:
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case Operation::CHK:
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return DataSize::Word;
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case Operation::ADDl: case Operation::ADDAl:
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case Operation::ADDXl: case Operation::SUBl:
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case Operation::SUBAl: case Operation::SUBXl:
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case Operation::MOVEl: case Operation::MOVEAl:
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case Operation::LEA: case Operation::PEA:
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case Operation::EXG: case Operation::SWAP:
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case Operation::MOVEtoUSP:
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case Operation::MOVEfromUSP:
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case Operation::CMPl: case Operation::CMPAl:
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case Operation::TSTl:
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case Operation::JMP: case Operation::JSR:
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case Operation::RTS:
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case Operation::Bccl: case Operation::BSRl:
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case Operation::CLRl:
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case Operation::NEGXl: case Operation::NEGl:
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case Operation::ASLl: case Operation::ASRl:
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case Operation::LSLl: case Operation::LSRl:
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case Operation::ROLl: case Operation::RORl:
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case Operation::ROXLl: case Operation::ROXRl:
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case Operation::MOVEPl:
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case Operation::ANDl: case Operation::EORl:
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case Operation::NOTl: case Operation::ORl:
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case Operation::EXTwtol:
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case Operation::UNLINK:
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return DataSize::LongWord;
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}
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}
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}
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}
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#endif /* InstructionSets_68k_InstructionOperandSize_hpp */
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@ -133,107 +133,7 @@ enum class DataSize {
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/// For any operations that don't fit the neat model of reading one or two operands,
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/// then writing zero or one, the size determines the data size of the operands only,
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/// not any other accesses.
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constexpr DataSize operand_size(Operation operation) {
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switch(operation) {
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// These are given a value arbitrarily, to
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// complete the switch statement.
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case Operation::Undefined:
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case Operation::NOP:
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case Operation::STOP:
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case Operation::RESET:
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case Operation::RTE: case Operation::RTR:
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case Operation::TRAP:
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case Operation::TRAPV:
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case Operation::ABCD: case Operation::SBCD:
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case Operation::NBCD:
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case Operation::ADDb: case Operation::ADDXb:
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case Operation::SUBb: case Operation::SUBXb:
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case Operation::MOVEb:
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case Operation::ORItoCCR:
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case Operation::ANDItoCCR:
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case Operation::EORItoCCR:
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case Operation::BTST: case Operation::BCLR:
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case Operation::BCHG: case Operation::BSET:
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case Operation::CMPb: case Operation::TSTb:
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case Operation::Bccb: case Operation::BSRb:
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case Operation::CLRb:
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case Operation::Scc:
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case Operation::NEGXb: case Operation::NEGb:
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case Operation::ASLb: case Operation::ASRb:
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case Operation::LSLb: case Operation::LSRb:
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case Operation::ROLb: case Operation::RORb:
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case Operation::ROXLb: case Operation::ROXRb:
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case Operation::ANDb: case Operation::EORb:
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case Operation::NOTb: case Operation::ORb:
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case Operation::TAS:
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return DataSize::Byte;
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case Operation::ADDw: case Operation::ADDAw:
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case Operation::ADDXw: case Operation::SUBw:
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case Operation::SUBAw: case Operation::SUBXw:
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case Operation::MOVEw: case Operation::MOVEAw:
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case Operation::ORItoSR:
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case Operation::ANDItoSR:
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case Operation::EORItoSR:
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case Operation::MOVEtoSR:
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case Operation::MOVEfromSR:
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case Operation::MOVEtoCCR:
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case Operation::CMPw: case Operation::CMPAw:
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case Operation::TSTw:
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case Operation::DBcc:
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case Operation::Bccw: case Operation::BSRw:
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case Operation::CLRw:
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case Operation::NEGXw: case Operation::NEGw:
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case Operation::ASLw: case Operation::ASLm:
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case Operation::ASRw: case Operation::ASRm:
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case Operation::LSLw: case Operation::LSLm:
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case Operation::LSRw: case Operation::LSRm:
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case Operation::ROLw: case Operation::ROLm:
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case Operation::RORw: case Operation::RORm:
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case Operation::ROXLw: case Operation::ROXLm:
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case Operation::ROXRw: case Operation::ROXRm:
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case Operation::MOVEMtoRw:
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case Operation::MOVEMtoRl:
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case Operation::MOVEMtoMw:
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case Operation::MOVEMtoMl:
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case Operation::MOVEPw:
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case Operation::ANDw: case Operation::EORw:
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case Operation::NOTw: case Operation::ORw:
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case Operation::DIVU: case Operation::DIVS:
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case Operation::MULU: case Operation::MULS:
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case Operation::EXTbtow:
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case Operation::LINKw:
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case Operation::CHK:
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return DataSize::Word;
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case Operation::ADDl: case Operation::ADDAl:
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case Operation::ADDXl: case Operation::SUBl:
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case Operation::SUBAl: case Operation::SUBXl:
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case Operation::MOVEl: case Operation::MOVEAl:
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case Operation::LEA: case Operation::PEA:
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case Operation::EXG: case Operation::SWAP:
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case Operation::MOVEtoUSP:
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case Operation::MOVEfromUSP:
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case Operation::CMPl: case Operation::CMPAl:
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case Operation::TSTl:
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case Operation::JMP: case Operation::JSR:
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case Operation::RTS:
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case Operation::Bccl: case Operation::BSRl:
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case Operation::CLRl:
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case Operation::NEGXl: case Operation::NEGl:
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case Operation::ASLl: case Operation::ASRl:
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case Operation::LSLl: case Operation::LSRl:
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case Operation::ROLl: case Operation::RORl:
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case Operation::ROXLl: case Operation::ROXRl:
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case Operation::MOVEPl:
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case Operation::ANDl: case Operation::EORl:
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case Operation::NOTl: case Operation::ORl:
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case Operation::EXTwtol:
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case Operation::UNLINK:
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return DataSize::LongWord;
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}
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}
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constexpr DataSize operand_size(Operation operation);
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template <Operation t_op = Operation::Undefined>
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constexpr uint32_t quick(uint16_t instruction, Operation r_op = Operation::Undefined) {
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@ -261,133 +161,10 @@ static constexpr uint8_t StoreOp2 = (1 << 3);
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Unusual bus sequences, such as TAS or MOVEM, are not described here.
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*/
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template <Model model, Operation t_operation = Operation::Undefined> uint8_t operand_flags(Operation r_operation = Operation::Undefined) {
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switch((t_operation != Operation::Undefined) ? t_operation : r_operation) {
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default:
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assert(false);
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//
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// No operands are fetched or stored.
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// (which means that source and destination will appear as their effective addresses)
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//
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case Operation::PEA:
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case Operation::JMP: case Operation::JSR:
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case Operation::MOVEPw: case Operation::MOVEPl:
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case Operation::MOVEMtoMw: case Operation::MOVEMtoMl:
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case Operation::MOVEMtoRw: case Operation::MOVEMtoRl:
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case Operation::TAS:
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case Operation::RTR: case Operation::RTS: case Operation::RTE:
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return 0;
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//
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// Single-operand read.
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//
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case Operation::MOVEtoSR: case Operation::MOVEtoCCR: case Operation::MOVEtoUSP:
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case Operation::ORItoSR: case Operation::ORItoCCR:
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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case Operation::EORItoSR: case Operation::EORItoCCR:
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case Operation::Bccb: case Operation::Bccw: case Operation::Bccl:
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case Operation::BSRb: case Operation::BSRw: case Operation::BSRl:
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case Operation::TSTb: case Operation::TSTw: case Operation::TSTl:
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return FetchOp1;
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//
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// Single-operand write.
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//
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case Operation::MOVEfromSR: case Operation::MOVEfromUSP:
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case Operation::Scc:
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return StoreOp1;
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//
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// Single-operand read-modify-write.
|
||||
//
|
||||
case Operation::NBCD:
|
||||
case Operation::NOTb: case Operation::NOTw: case Operation::NOTl:
|
||||
case Operation::NEGb: case Operation::NEGw: case Operation::NEGl:
|
||||
case Operation::NEGXb: case Operation::NEGXw: case Operation::NEGXl:
|
||||
case Operation::EXTbtow: case Operation::EXTwtol:
|
||||
case Operation::SWAP:
|
||||
case Operation::UNLINK:
|
||||
case Operation::ASLm: case Operation::ASRm:
|
||||
case Operation::LSLm: case Operation::LSRm:
|
||||
case Operation::ROLm: case Operation::RORm:
|
||||
case Operation::ROXLm: case Operation::ROXRm:
|
||||
return FetchOp1 | StoreOp1;
|
||||
|
||||
//
|
||||
// CLR, which is model-dependent.
|
||||
//
|
||||
case Operation::CLRb: case Operation::CLRw: case Operation::CLRl:
|
||||
if constexpr (model == Model::M68000) {
|
||||
return FetchOp1 | StoreOp1;
|
||||
} else {
|
||||
return StoreOp1;
|
||||
}
|
||||
|
||||
//
|
||||
// Two-operand; read both.
|
||||
//
|
||||
case Operation::CMPb: case Operation::CMPw: case Operation::CMPl:
|
||||
case Operation::CMPAw: case Operation::CMPAl:
|
||||
case Operation::CHK:
|
||||
case Operation::BTST:
|
||||
case Operation::LINKw:
|
||||
return FetchOp1 | FetchOp2;
|
||||
|
||||
//
|
||||
// Two-operand; read source, write dest.
|
||||
//
|
||||
case Operation::MOVEb: case Operation::MOVEw: case Operation::MOVEl:
|
||||
case Operation::MOVEAw: case Operation::MOVEAl:
|
||||
return FetchOp1 | StoreOp2;
|
||||
|
||||
//
|
||||
// Two-operand; read both, write dest.
|
||||
//
|
||||
case Operation::ABCD: case Operation::SBCD:
|
||||
case Operation::ADDb: case Operation::ADDw: case Operation::ADDl:
|
||||
case Operation::ADDAw: case Operation::ADDAl:
|
||||
case Operation::ADDXb: case Operation::ADDXw: case Operation::ADDXl:
|
||||
case Operation::SUBb: case Operation::SUBw: case Operation::SUBl:
|
||||
case Operation::SUBAw: case Operation::SUBAl:
|
||||
case Operation::SUBXb: case Operation::SUBXw: case Operation::SUBXl:
|
||||
case Operation::ORb: case Operation::ORw: case Operation::ORl:
|
||||
case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
|
||||
case Operation::EORb: case Operation::EORw: case Operation::EORl:
|
||||
case Operation::DIVU: case Operation::DIVS:
|
||||
case Operation::MULU: case Operation::MULS:
|
||||
case Operation::ASLb: case Operation::ASLw: case Operation::ASLl:
|
||||
case Operation::ASRb: case Operation::ASRw: case Operation::ASRl:
|
||||
case Operation::LSLb: case Operation::LSLw: case Operation::LSLl:
|
||||
case Operation::LSRb: case Operation::LSRw: case Operation::LSRl:
|
||||
case Operation::ROLb: case Operation::ROLw: case Operation::ROLl:
|
||||
case Operation::RORb: case Operation::RORw: case Operation::RORl:
|
||||
case Operation::ROXLb: case Operation::ROXLw: case Operation::ROXLl:
|
||||
case Operation::ROXRb: case Operation::ROXRw: case Operation::ROXRl:
|
||||
case Operation::BCHG:
|
||||
case Operation::BCLR: case Operation::BSET:
|
||||
return FetchOp1 | FetchOp2 | StoreOp2;
|
||||
|
||||
//
|
||||
// Two-operand; read both, write source.
|
||||
//
|
||||
case Operation::DBcc:
|
||||
return FetchOp1 | FetchOp2 | StoreOp1;
|
||||
|
||||
//
|
||||
// Two-operand; read both, write both.
|
||||
//
|
||||
case Operation::EXG:
|
||||
return FetchOp1 | FetchOp2 | StoreOp1 | StoreOp2;
|
||||
|
||||
//
|
||||
// Two-operand; just write destination.
|
||||
//
|
||||
case Operation::LEA:
|
||||
return StoreOp2;
|
||||
}
|
||||
}
|
||||
template <Model model, Operation t_operation = Operation::Undefined>
|
||||
uint8_t operand_flags(Operation r_operation = Operation::Undefined);
|
||||
|
||||
/// Lists the various condition codes used by the 680x0.
|
||||
enum class Condition {
|
||||
True = 0x00, False = 0x01,
|
||||
High = 0x02, LowOrSame = 0x03,
|
||||
@ -554,4 +331,7 @@ class Preinstruction {
|
||||
}
|
||||
}
|
||||
|
||||
#include "Implementation/InstructionOperandSize.hpp"
|
||||
#include "Implementation/InstructionOperandFlags.hpp"
|
||||
|
||||
#endif /* InstructionSets_68k_Instruction_hpp */
|
||||
|
||||
@ -2044,6 +2044,8 @@
|
||||
4BC76E681C98E31700E6EF73 /* FIRFilter.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = FIRFilter.hpp; sourceTree = "<group>"; };
|
||||
4BC890D1230F86020025A55A /* DirectAccessDevice.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = DirectAccessDevice.cpp; sourceTree = "<group>"; };
|
||||
4BC890D2230F86020025A55A /* DirectAccessDevice.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = DirectAccessDevice.hpp; sourceTree = "<group>"; };
|
||||
4BC8C01028294C3A0018A501 /* InstructionOperandSize.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = InstructionOperandSize.hpp; sourceTree = "<group>"; };
|
||||
4BC8C01228294DEB0018A501 /* InstructionOperandFlags.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = InstructionOperandFlags.hpp; sourceTree = "<group>"; };
|
||||
4BC91B811D1F160E00884B76 /* CommodoreTAP.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = CommodoreTAP.cpp; sourceTree = "<group>"; };
|
||||
4BC91B821D1F160E00884B76 /* CommodoreTAP.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = CommodoreTAP.hpp; sourceTree = "<group>"; };
|
||||
4BC9DF441D044FCA00F44158 /* ROMImages */ = {isa = PBXFileReference; lastKnownFileType = folder; name = ROMImages; path = ../../../../ROMImages; sourceTree = "<group>"; };
|
||||
@ -4112,8 +4114,10 @@
|
||||
4BB5B999281B244400522DA9 /* Implementation */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4BB5B99A281B244400522DA9 /* PerformImplementation.hpp */,
|
||||
4BB5B99F281F121200522DA9 /* ExecutorImplementation.hpp */,
|
||||
4BC8C01228294DEB0018A501 /* InstructionOperandFlags.hpp */,
|
||||
4BC8C01028294C3A0018A501 /* InstructionOperandSize.hpp */,
|
||||
4BB5B99A281B244400522DA9 /* PerformImplementation.hpp */,
|
||||
);
|
||||
path = Implementation;
|
||||
sourceTree = "<group>";
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user