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https://github.com/TomHarte/CLK.git
synced 2024-07-03 11:30:02 +00:00
Implements further MOVEs and fixes a potential error in program formation.
This commit is contained in:
Thomas Harte
parent
2c5ff9ada0
commit
8f1faefa1c
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@ -971,6 +971,32 @@ struct ProcessorStorageConstructor {
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op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw);
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break;
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case 0x0204: // MOVE (An), -(An)
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case 0x0304: // MOVE (An)+, -(An)
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// nr np nw
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continue;
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case 0x0404: // MOVE -(An), -(An)
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// n nr np nw
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continue;
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case 0x0504: // MOVE (d16, An), -(An)
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case 0x0604: // MOVE (d8, An, Xn), -(An)
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// np nr np nw
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// n np nr np nw
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continue;
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case 0x1004: // MOVE (xxx).W, -(An)
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// np nr np nw
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continue;
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//
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// MOVE <ea>, (d16, An)
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// MOVE <ea>, (d8, An, Xn)
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// MOVE <ea>, (d16, An)
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// MOVE <ea>, (d16, An)
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//
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case 0x0005: // MOVE Dn, (d16, An)
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op(int(Action::CalcD16An) | MicroOp::DestinationMask, seq("np"));
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op(Action::PerformOperation, seq("nw np", { &storage_.effective_address_[1].full }));
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@ -981,41 +1007,6 @@ struct ProcessorStorageConstructor {
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op(Action::PerformOperation, seq("nw np", { &storage_.effective_address_[1].full }));
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break;
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case 0x0010: // MOVE Dn, (xxx).W
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op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask);
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op(Action::PerformOperation, seq("np nw np", { &storage_.effective_address_[1].full }));
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break;
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case 0x0011: // MOVE Dn, (xxx).L
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op(Action::None, seq("np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask);
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op(Action::PerformOperation, seq("np nw np", { &storage_.effective_address_[1].full }));
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break;
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case 0x0204: // MOVE (An), -(An)
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case 0x0304: // MOVE (An)+, -(An)
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// nr np nw
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continue;
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case 0x0404: // MOVE -(An), -(An)
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// n nr np nw
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continue;
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case 0x0504: // MOVE (d16, An), -(An)
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case 0x0604: // MOVE (d8, An, Xn), -(An)
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// np nr np nw
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// n np nr np nw
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continue;
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case 0x1004: // MOVE (xxx).W, -(An)
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// np nr np nw
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continue;
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//
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// Source = (An) or (An)+
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//
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case 0x0205: // MOVE (An), (d16, An)
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case 0x0305: // MOVE (An)+, (d16, An)
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// nr np nw np
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@ -1026,23 +1017,6 @@ struct ProcessorStorageConstructor {
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// nr n np nw np
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continue;
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case 0x0210: // MOVE (An), (xxx).W
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case 0x0310: // MOVE (An)+, (xxx).W
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// nr np nw np
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continue;
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case 0x0211: // MOVE (An), (xxx).L
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case 0x0311: // MOVE (An)+, (xxx).L
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// nr np nw np np
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continue;
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//
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// Source = -(An)
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//
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case 0x0405: // MOVE -(An), (d16, An)
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// n nr np nw
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continue;
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@ -1051,21 +1025,6 @@ struct ProcessorStorageConstructor {
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// n nr n np nw np
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continue;
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case 0x0410: // MOVE -(An), (xxx).W
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// n nr np nw np
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continue;
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case 0x0411: // MOVE -(An), (xxx).L
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// n nr np nw np np
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continue;
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//
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// Source = (d16, An) or (d8, An, Xn)
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//
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case 0x0505: // MOVE (d16, An), (d16, An)
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case 0x0605: // MOVE (d8, An, Xn), (d16, An)
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// np nr np nw np
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@ -1078,25 +1037,6 @@ struct ProcessorStorageConstructor {
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// n np nr n np nw np
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continue;
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case 0x0510: // MOVE (d16, An), (xxx).W
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case 0x0610: // MOVE (d8, An, Xn), (xxx).W
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// np nr np nw np
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// n np nr np nw np
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continue;
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case 0x0511: // MOVE (d16, An), (xxx).L
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case 0x0611: // MOVE (d8, An, Xn), (xxx).L
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// np nr np nw np np
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// n np nr np nw np np
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continue;
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//
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// Source = (xxx).W
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//
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case 0x1005: // MOVE (xxx).W, (d16, An)
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// np nr np nw np
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continue;
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@ -1105,41 +1045,30 @@ struct ProcessorStorageConstructor {
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// np nr n np nw np
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continue;
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case 0x1010: // MOVE (xxx).W, (xxx).W
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// np nr np nw np
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continue;
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case 0x1011: // MOVE (xxx).W, (xxx).L
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// np nr np nw np np
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continue;
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//
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// Source = (xxx).L
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// MOVE <ea>, (xxx).W
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//
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//
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// Source = (d16, PC)
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//
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//
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// Source = (d8, An, Xn)
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//
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//
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// Source = #
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//
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case 0x11411: // MOVE.l #, (xxx).l
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op(int(Action::None), seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW nw np", { &storage_.effective_address_[1].full }));
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op(Action::SetMoveFlagsl);
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case 0x0010: // MOVE Dn, (xxx).W
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op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np"));
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op(Action::PerformOperation, seq("nw np", { &storage_.effective_address_[1].full }));
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break;
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case 0x0210: // MOVE (An), (xxx).W
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case 0x0310: // MOVE (An)+, (xxx).W
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// nr np nw np
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continue;
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case 0x0410: // MOVE -(An), (xxx).W
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// n nr np nw np
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continue;
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case 0x0510: // MOVE (d16, An), (xxx).W
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case 0x0610: // MOVE (d8, An, Xn), (xxx).W
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// np nr np nw np
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// n np nr np nw np
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continue;
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case 0x11410: // MOVE.l #, (xxx).w
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op(int(Action::None), seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np"));
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@ -1147,16 +1076,82 @@ struct ProcessorStorageConstructor {
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op(Action::SetMoveFlagsl);
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break;
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case 0x1010: // MOVE (xxx).W, (xxx).W
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// np nr np nw np
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continue;
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case 0x01410: // MOVE.bw #, (xxx).w
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np"));
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op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { &storage_.effective_address_[1].full }, !is_byte_access));
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op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw);
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break;
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//
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// MOVE <ea>, (xxx).L
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//
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case 0x00011: // MOVE.bw Dn, (xxx).L
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op(Action::None, seq("np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np"));
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op(Action::PerformOperation, seq("nw np", { &storage_.effective_address_[1].full }, !is_byte_access));
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break;
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case 0x00211: // MOVE.bw (An), (xxx).L
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case 0x00311: // MOVE.bw (An)+, (xxx).L
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op(Action::None, seq("nr np", { &storage_.address_[source_register].full }, !is_byte_access));
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op(Action::PerformOperation, seq("nw np np", { &storage_.prefetch_queue_.full }));
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if(source_mode == 0x3) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::SourceMask);
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}
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break;
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case 0x0411: // MOVE -(An), (xxx).L
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// n nr np nw np np
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continue;
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case 0x0511: // MOVE (d16, An), (xxx).L
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case 0x0611: // MOVE (d8, An, Xn), (xxx).L
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// np nr np nw np np
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// n np nr np nw np np
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continue;
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case 0x01011: // MOVE.bw (xxx).W, (xxx).L
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op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::SourceMask, seq("np nr", { &storage_.effective_address_[0].full }, !is_byte_access));
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op(Action::PerformOperation, seq("np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("nw np np", { &storage_.effective_address_[1].full }, !is_byte_access));
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continue;
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case 0x01111: // MOVE.bw (xxx).l, (xxx).l
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op(int(Action::None), seq("np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::SourceMask, seq("np nr", { &storage_.effective_address_[0].full }, !is_byte_access));
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op(Action::PerformOperation, seq("np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("nw np np", { &storage_.effective_address_[1].full }, !is_byte_access));
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break;
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case 0x01411: // MOVE.bw #, (xxx).l
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { &storage_.effective_address_[1].full }));
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op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw);
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break;
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case 0x01410: // MOVE.bw #, (xxx).w
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np"));
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op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { &storage_.effective_address_[1].full }, !is_byte_access));
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op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw);
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case 0x11011: // MOVE.l (xxx).W, (xxx).L
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op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::SourceMask, seq("np nR nr", { &storage_.effective_address_[0].full }));
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op(Action::PerformOperation, seq("np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("nW nw np np", { &storage_.effective_address_[1].full }));
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break;
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case 0x11111: // MOVE.l (xxx).l, (xxx).l
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op(int(Action::None), seq("np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::SourceMask, seq("np nR nr", { &storage_.effective_address_[0].full }));
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op(Action::PerformOperation, seq("np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("nW nw np np", { &storage_.effective_address_[1].full }));
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break;
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case 0x11411: // MOVE.l #, (xxx).l
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op(int(Action::None), seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW nw np", { &storage_.effective_address_[1].full }));
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op(Action::SetMoveFlagsl);
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break;
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//
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@ -1185,6 +1180,13 @@ struct ProcessorStorageConstructor {
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storage_.all_micro_ops_.emplace_back();
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}
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// Ensure that steps that weren't meant to look terminal aren't terminal.
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for(auto index = micro_op_start; index < storage_.all_micro_ops_.size() - 1; ++index) {
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if(storage_.all_micro_ops_[index].is_terminal()) {
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storage_.all_micro_ops_[index].bus_program = seq("");
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}
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}
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// Install the operation and make a note of where micro-ops begin.
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storage_.instructions[instruction].operation = operation;
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micro_op_pointers[instruction] = micro_op_start;
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@ -1258,4 +1260,3 @@ void CPU::MC68000::ProcessorStorage::set_is_supervisor(bool is_supervisor) {
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address_[7] = stack_pointers_[is_supervisor_];
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}
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}
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