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Attempt IRQ logic.
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parent
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commit
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@ -82,10 +82,18 @@ class FloppyController {
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break;
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break;
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case Command::SenseInterruptStatus:
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case Command::SenseInterruptStatus:
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pic_.apply_edge<6>(false);
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results_.serialise_none();
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results_.serialise_none();
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break;
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break;
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}
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}
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// Set interrupt upon the end of any valid command other than sense interrupt status.
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if(decoder_.command() != Command::SenseInterruptStatus && decoder_.command() != Command::Invalid) {
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pic_.apply_edge<6>(true);
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}
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decoder_.clear();
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// If there are any results to provide, set data direction and data ready.
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if(!results_.empty()) {
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if(!results_.empty()) {
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using MainStatus = Intel::i8272::MainStatus;
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using MainStatus = Intel::i8272::MainStatus;
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status_.set(MainStatus::DataIsToProcessor, true);
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status_.set(MainStatus::DataIsToProcessor, true);
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@ -112,6 +120,10 @@ class FloppyController {
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decoder_.clear();
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decoder_.clear();
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status_.reset();
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status_.reset();
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pic_.apply_edge<6>(true);
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pic_.apply_edge<6>(true);
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using MainStatus = Intel::i8272::MainStatus;
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status_.set(MainStatus::DataReady, true);
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status_.set(MainStatus::DataIsToProcessor, false);
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}
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}
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PIC &pic_;
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PIC &pic_;
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