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Implements TSB and TRB, and adds the extra BIT instructions.

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This commit is contained in:
Thomas Harte 2018-08-10 22:04:45 -04:00
parent aed4c0539e
commit 90094529a5
4 changed files with 33 additions and 2 deletions
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4
OSBindings/Mac/Clock SignalTests/KlausDormannTests.swift
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@ -90,6 +90,10 @@ class KlausDormannTests: XCTestCase {
case 0x1983: return "STZ didn't store zero" case 0x1983: return "STZ didn't store zero"
case 0x1b03: return "BIT didn't set flags correctly" case 0x1b03: return "BIT didn't set flags correctly"
case 0x1c6c: return "BIT immediate didn't set flags correctly"
case 0x1d88: return "TRB set Z flag incorrectly"
case 0x1e7c: return "RMB set flags incorrectly"
case 0: return "Didn't find tests" case 0: return "Didn't find tests"
default: return "Unknown error at \(String(format:"%04x", address))" default: return "Unknown error at \(String(format:"%04x", address))"

16
Processors/6502/Implementation/6502Implementation.hpp
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@ -108,6 +108,9 @@ if(number_of_cycles <= Cycles(0)) break;
break; break;
case OperationDecodeOperation: case OperationDecodeOperation:
if(operation_ == 0x89) {
printf("");
}
scheduled_program_counter_ = operations_[operation_]; scheduled_program_counter_ = operations_[operation_];
continue; continue;
@ -231,13 +234,24 @@ if(number_of_cycles <= Cycles(0)) break;
carry_flag_ = ((~temp16) >> 8)&1; carry_flag_ = ((~temp16) >> 8)&1;
} continue; } continue;
// MARK: - BIT // MARK: - BIT, TSB, TRB
case OperationBIT: case OperationBIT:
zero_result_ = operand_ & a_; zero_result_ = operand_ & a_;
negative_result_ = operand_; negative_result_ = operand_;
overflow_flag_ = operand_&Flag::Overflow; overflow_flag_ = operand_&Flag::Overflow;
continue; continue;
case OperationBITNoNV:
zero_result_ = operand_ & a_;
continue;
case OperationTRB:
zero_result_ = operand_ & a_;
operand_ &= ~a_;
continue;
case OperationTSB:
zero_result_ = operand_ & a_;
operand_ |= a_;
continue;
// MARK: - ADC/SBC (and INS) // MARK: - ADC/SBC (and INS)

11
Processors/6502/Implementation/6502Storage.cpp
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@ -292,6 +292,17 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
Install(0x9e, AbsoluteXWrite(OperationSTZ)); Install(0x9e, AbsoluteXWrite(OperationSTZ));
Install(0x64, ZeroWrite(OperationSTZ)); Install(0x64, ZeroWrite(OperationSTZ));
Install(0x74, ZeroXWrite(OperationSTZ)); Install(0x74, ZeroXWrite(OperationSTZ));
// Add the extra BITs.
Install(0x34, ZeroXRead(OperationBIT));
Install(0x3c, AbsoluteXRead(OperationBIT));
Install(0x89, Immediate(OperationBITNoNV));
// Add TRB and TSB.
Install(0x04, ZeroReadModifyWrite(OperationTSB));
Install(0x0c, AbsoluteReadModifyWrite(OperationTSB));
Install(0x14, ZeroReadModifyWrite(OperationTRB));
Install(0x1c, AbsoluteReadModifyWrite(OperationTRB));
} }
#undef Install #undef Install
} }

4
Processors/6502/Implementation/6502Storage.hpp
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@ -52,11 +52,13 @@ class ProcessorStorage {
OperationSTX, OperationSTY, OperationSTZ, OperationSTX, OperationSTY, OperationSTZ,
OperationSAX, OperationSHA, OperationSAX, OperationSHA,
OperationSHX, OperationSHY, OperationSHS, OperationCMP, OperationSHX, OperationSHY, OperationSHS, OperationCMP,
OperationCPX, OperationCPY, OperationBIT, OperationASL, OperationCPX, OperationCPY, OperationBIT, OperationBITNoNV,
OperationASL,
OperationASO, OperationROL, OperationRLA, OperationLSR, OperationASO, OperationROL, OperationRLA, OperationLSR,
OperationLSE, OperationASR, OperationROR, OperationRRA, OperationLSE, OperationASR, OperationROR, OperationRRA,
OperationCLC, OperationCLI, OperationCLV, OperationCLD, OperationCLC, OperationCLI, OperationCLV, OperationCLD,
OperationSEC, OperationSEI, OperationSED, OperationSEC, OperationSEI, OperationSED,
OperationTRB, OperationTSB,
OperationINC, OperationDEC, OperationINX, OperationDEX, OperationINC, OperationDEC, OperationINX, OperationDEX,
OperationINY, OperationDEY, OperationINA, OperationDEA, OperationINY, OperationDEY, OperationINA, OperationDEA,