mirror of
https://github.com/TomHarte/CLK.git
synced 2025-01-11 08:30:55 +00:00
Documents all 6502 micro-operations.
Also makes sure 1-cycle NOPs really, definitely are one cycle only on a 65C02 and eliminates OperationCopyOperandFromA as a redundant copy of OperationSTA.
This commit is contained in:
Thomas Harte
parent
ddf45a0010
commit
901e0d65b9
@ -104,6 +104,9 @@ if(number_of_cycles <= Cycles(0)) break;
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operation_ == 0xdb
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) {
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read_mem(operand_, pc_.full);
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break;
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} else {
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continue;
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}
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break;
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@ -173,11 +176,11 @@ if(number_of_cycles <= Cycles(0)) break;
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case OperationSetFlagsFromX: zero_result_ = negative_result_ = x_; continue;
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case OperationSetFlagsFromY: zero_result_ = negative_result_ = y_; continue;
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case CycleIncrementPCAndReadStack: pc_.full++; throwaway_read(s_ | 0x100); break;
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case CycleReadPCLFromAddress: read_mem(pc_.bytes.low, address_.full); break;
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case CycleReadPCHFromAddressLowInc: address_.bytes.low++; read_mem(pc_.bytes.high, address_.full); break;
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case CycleReadPCHFromAddressFixed: if(!address_.bytes.low) address_.bytes.high++; read_mem(pc_.bytes.high, address_.full); break;
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case CycleReadPCHFromAddressInc: address_.full++; read_mem(pc_.bytes.high, address_.full); break;
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case CycleIncrementPCAndReadStack: pc_.full++; throwaway_read(s_ | 0x100); break;
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case CycleReadPCLFromAddress: read_mem(pc_.bytes.low, address_.full); break;
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case CycleReadPCHFromAddressLowInc: address_.bytes.low++; read_mem(pc_.bytes.high, address_.full); break;
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case CycleReadPCHFromAddressFixed: if(!address_.bytes.low) address_.bytes.high++; read_mem(pc_.bytes.high, address_.full); break;
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case CycleReadPCHFromAddressInc: address_.full++; read_mem(pc_.bytes.high, address_.full); break;
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case CycleReadAndIncrementPC: {
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uint16_t oldPC = pc_.full;
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@ -204,6 +207,7 @@ if(number_of_cycles <= Cycles(0)) break;
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case OperationLDX: x_ = negative_result_ = zero_result_ = operand_; continue;
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case OperationLDY: y_ = negative_result_ = zero_result_ = operand_; continue;
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case OperationLAX: a_ = x_ = negative_result_ = zero_result_ = operand_; continue;
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case OperationCopyOperandToA: a_ = operand_; continue;
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case OperationSTA: operand_ = a_; continue;
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case OperationSTX: operand_ = x_; continue;
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@ -516,8 +520,6 @@ if(number_of_cycles <= Cycles(0)) break;
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case OperationIncrementPC: pc_.full++; continue;
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case CycleFetchOperandFromAddress: read_mem(operand_, address_.full); break;
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case CycleWriteOperandToAddress: write_mem(operand_, address_.full); break;
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case OperationCopyOperandFromA: operand_ = a_; continue;
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case OperationCopyOperandToA: a_ = operand_; continue;
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// MARK: - Branching
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@ -61,7 +61,7 @@ using namespace CPU::MOS6502;
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#define IndirectIndexedReadModifyWrite(...) Program(IndirectIndexed, ReadModifyWrite(__VA_ARGS__))
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#define Immediate(op) Program(OperationIncrementPC, op)
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#define Implied(op) Program(OperationCopyOperandFromA, op, OperationCopyOperandToA)
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#define Implied(op) Program(OperationSTA, op, OperationCopyOperandToA)
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#define ZeroNop() Program(Zero, CycleFetchOperandFromAddress)
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#define ZeroXNop() Program(ZeroX, CycleFetchOperandFromAddress)
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@ -23,62 +23,173 @@ class ProcessorStorage {
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to perform whereas those called OperationX occur for free (so, in effect, their cost is loaded onto the next cycle).
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*/
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enum MicroOp {
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CycleFetchOperation, CycleFetchOperand, OperationDecodeOperation, CycleIncPCPushPCH,
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CyclePushPCH, CyclePushPCL, CyclePushA, CyclePushOperand,
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CyclePushX, CyclePushY, OperationSetIRQFlags, OperationSetNMIRSTFlags,
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CycleFetchOperation, // fetches (PC) to operation_, storing PC to last_operation_pc_ before incrementing it
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CycleFetchOperand, // 6502: fetches from (PC) to operand_; 65C02: as 6502 unless operation_ indicates a one-cycle NOP, in which case this is a no0op
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OperationDecodeOperation, // schedules the microprogram associated with operation_
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OperationMoveToNextProgram, // either schedules the next fetch-decode-execute or an interrupt response if a request has been pending for at least one cycle
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OperationBRKPickVector, OperationNMIPickVector, OperationRSTPickVector,
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CycleReadVectorLow, CycleReadVectorHigh,
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CycleIncPCPushPCH, // increments the PC and pushes PC.h to the stack
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CyclePushPCL, // pushes PC.l to the stack
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CyclePushPCH, // pushes PC.h to the stack
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CyclePushA, // pushes A to the stack
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CyclePushX, // pushes X to the stack
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CyclePushY, // pushes Y to the stack
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CyclePushOperand, // pushes operand_ to the stack
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CycleReadFromS, CycleReadFromPC,
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CyclePullOperand, CyclePullPCL, CyclePullPCH, CyclePullA,
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CyclePullX, CyclePullY,
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CycleNoWritePush,
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CycleReadAndIncrementPC, CycleIncrementPCAndReadStack, CycleIncrementPCReadPCHLoadPCL, CycleReadPCHLoadPCL,
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CycleReadAddressHLoadAddressL,
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OperationSetIRQFlags, // 6502: sets I; 65C02: sets I and resets D
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OperationSetNMIRSTFlags, // 6502: no-op. 65C02: resets D
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CycleReadPCLFromAddress, CycleReadPCHFromAddressLowInc, CycleReadPCHFromAddressFixed, CycleReadPCHFromAddressInc,
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OperationBRKPickVector, // 65C02: sets next_address_ to the BRK vector location; 6502: as 65C02 if no NMI is pending; otherwise sets next_address_ to the NMI address and resets the internal NMI-pending flag
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OperationNMIPickVector, // sets next_address_ to the NMI vector
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OperationRSTPickVector, // sets next_address_ to the RST vector
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CycleReadVectorLow, // reads PC.l from next_address_
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CycleReadVectorHigh, // reads PC.h from (next_address_+1)
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CycleLoadAddressAbsolute,
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OperationLoadAddressZeroPage, CycleLoadAddessZeroX, CycleLoadAddessZeroY, CycleAddXToAddressLow,
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CycleAddYToAddressLow, CycleAddXToAddressLowRead, OperationCorrectAddressHigh, CycleAddYToAddressLowRead,
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OperationMoveToNextProgram, OperationIncrementPC,
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CycleFetchOperandFromAddress, CycleWriteOperandToAddress, OperationCopyOperandFromA, OperationCopyOperandToA,
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CycleIncrementPCFetchAddressLowFromOperand, CycleAddXToOperandFetchAddressLow, CycleIncrementOperandFetchAddressHigh, OperationDecrementOperand,
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CycleFetchAddressLowFromOperand,
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OperationIncrementOperand, OperationORA, OperationAND, OperationEOR,
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OperationINS, OperationADC, OperationSBC, OperationLDA,
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OperationLDX, OperationLDY, OperationLAX, OperationSTA,
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OperationSTX, OperationSTY, OperationSTZ,
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OperationSAX, OperationSHA,
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OperationSHX, OperationSHY, OperationSHS, OperationCMP,
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OperationCPX, OperationCPY, OperationBIT, OperationBITNoNV,
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OperationASL, OperationRMB, OperationSMB,
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OperationASO, OperationROL, OperationRLA, OperationLSR,
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OperationLSE, OperationASR, OperationROR, OperationRRA,
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OperationCLC, OperationCLI, OperationCLV, OperationCLD,
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OperationSEC, OperationSEI, OperationSED,
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OperationTRB, OperationTSB,
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CycleReadFromS, // performs a read from the stack pointer, throwing the result away
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CycleReadFromPC, // performs a read from the program counter, throwing the result away
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OperationINC, OperationDEC, OperationINX, OperationDEX,
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OperationINY, OperationDEY, OperationINA, OperationDEA,
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CyclePullPCL, // pulls PC.l from the stack
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CyclePullPCH, // pulls PC.h from the stack
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CyclePullA, // pulls A from the stack
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CyclePullX, // pulls X from the stack
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CyclePullY, // pulls Y from the stack
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CyclePullOperand, // pulls operand_ from the stack
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OperationBPL, OperationBMI, OperationBVC, OperationBVS,
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OperationBCC, OperationBCS, OperationBNE, OperationBEQ,
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OperationBRA, OperationBBRBBS,
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CycleNoWritePush, // decrements S as though it were a push, but reads from the new stack address instead of writing
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CycleReadAndIncrementPC, // reads from the PC, throwing away the result, and increments the PC
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CycleIncrementPCAndReadStack, // increments the PC and reads from the stack pointer, throwing away the result
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CycleIncrementPCReadPCHLoadPCL, // increments the PC, schedules a read of PC.h from the post-incremented PC, then copies operand_ to PC.l
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CycleReadPCHLoadPCL, // schedules a read of PC.h from the post-incremented PC, then copies operand_ to PC.l
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CycleReadAddressHLoadAddressL, // increments the PC; copies operand_ to address_.l; reads address_.h from the new PC
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OperationTXA, OperationTYA, OperationTXS, OperationTAY,
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OperationTAX, OperationTSX,
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CycleReadPCLFromAddress, // reads PC.l from address_
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CycleReadPCHFromAddressLowInc, // increments address_.l and reads PC.h from address_
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CycleReadPCHFromAddressFixed, // if address_.l is 0, increments address_.h; and reads PC.h from address_
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CycleReadPCHFromAddressInc, // increments address_ and reads PC.h from it
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OperationARR, OperationSBX, OperationLXA, OperationANE,
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OperationANC, OperationLAS,
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CycleLoadAddressAbsolute, // copies operand_ to address_.l, increments the PC, reads address_.h from PC, increments the PC again
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OperationLoadAddressZeroPage, // copies operand_ to address_ and increments the PC
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CycleLoadAddessZeroX, // copies (operand_+x)&0xff to address_, increments the PC, and reads from operand_, throwing away the result
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CycleLoadAddessZeroY, // copies (operand_+y)&0xff to address_, increments the PC, and reads from operand_, throwing away the result
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CycleFetchFromHalfUpdatedPC, CycleAddSignedOperandToPC, OperationAddSignedOperandToPC16,
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CycleAddXToAddressLow, // calculates address_ + x and stores it to next_address_; copies next_address_.l back to address_.l; if address_ now does not equal next_address_, schedules a throwaway read from address_
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CycleAddYToAddressLow, // calculates address_ + y and stores it to next_address_; copies next_address_.l back to address_.l; if address_ now does not equal next_address_, schedules a throwaway read from address_
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CycleAddXToAddressLowRead, // calculates address_ + x and stores it to next_address; copies next_address.l back to address_.l; schedules a throwaway read from address_
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CycleAddYToAddressLowRead, // calculates address_ + y and stores it to next_address; copies next_address.l back to address_.l; schedules a throwaway read from address_
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OperationCorrectAddressHigh, // copies next_address_ to address_
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OperationSetFlagsFromOperand, OperationSetOperandFromFlagsWithBRKSet,
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OperationSetOperandFromFlags,
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OperationSetFlagsFromA, OperationSetFlagsFromX, OperationSetFlagsFromY,
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CycleScheduleJam
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OperationIncrementPC, // increments the PC
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CycleFetchOperandFromAddress, // fetches operand_ from address_
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CycleWriteOperandToAddress, // writes operand_ to address_
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CycleIncrementPCFetchAddressLowFromOperand, // increments the PC and loads address_.l from (operand_)
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CycleAddXToOperandFetchAddressLow, // adds x [in]to operand_, producing an 8-bit result, and reads address_.l from (operand_)
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CycleIncrementOperandFetchAddressHigh, // increments operand_, producing an 8-bit result, and reads address_.h from (operand_)
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OperationDecrementOperand, // decrements operand_
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OperationIncrementOperand, // increments operand_
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CycleFetchAddressLowFromOperand, // reads address_.l from (operand_)
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OperationORA, // ORs operand_ into a, setting the negative and zero flags
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OperationAND, // ANDs operand_ into a, setting the negative and zero flags
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OperationEOR, // EORs operand_ into a, setting the negative and zero flags
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OperationINS, // increments operand_, then performs an SBC of operand_ from a
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OperationADC, // performs an ADC of operand_ into a_; if this is a 65C02 and decimal mode is set, performs an extra read to operand_ from address_
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OperationSBC, // performs an SBC of operand_ from a_; if this is a 65C02 and decimal mode is set, performs an extra read to operand_ from address_
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OperationCMP, // CMPs a and operand_, setting negative, zero and carry flags
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OperationCPX, // CMPs x and operand_, setting negative, zero and carry flags
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OperationCPY, // CMPs y and operand_, setting negative, zero and carry flags
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OperationBIT, // sets the zero, negative and overflow flags as per a BIT of operand_ against a
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OperationBITNoNV, // sets the zero flag as per a BIT of operand_ against a
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OperationLDA, // loads a with operand_, setting the negative and zero flags
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OperationLDX, // loads x with operand_, setting the negative and zero flags
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OperationLDY, // loads y with operand_, setting the negative and zero flags
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OperationLAX, // loads a and x with operand_, setting the negative and zero flags
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OperationCopyOperandToA, // sets a_ = operand_, not setting any flags
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OperationSTA, // loads operand_ with a
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OperationSTX, // loads operand_ with x
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OperationSTY, // loads operand_ with y
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OperationSTZ, // loads operand_ with 0
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OperationSAX, // loads operand_ with a & x
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OperationSHA, // loads operand_ with a & x & (address.h+1)
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OperationSHX, // loads operand_ with x & (address.h+1)
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OperationSHY, // loads operand_ with y & (address.h+1)
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OperationSHS, // loads s with a & x, then loads operand_ with s & (address.h+1)
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OperationASL, // shifts operand_ left, moving the top bit into carry and setting the negative and zero flags
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OperationASO, // performs an ASL of operand and ORs it into a
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OperationROL, // performs a ROL of operand_
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OperationRLA, // performs a ROL of operand_ and ANDs it into a
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OperationLSR, // shifts operand_ right, setting carry, negative and zero flags
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OperationLSE, // performs an LSR and EORs the result into a
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OperationASR, // ANDs operand_ into a, then performs an LSR
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OperationROR, // performs a ROR of operand_, setting carry, negative and zero flags
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OperationRRA, // performs a ROR of operand_ but sets only the carry flag
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OperationCLC, // resets the carry flag
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OperationCLI, // resets I
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OperationCLV, // resets the overflow flag
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OperationCLD, // resets the decimal flag
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OperationSEC, // sets the carry flag
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OperationSEI, // sets I
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OperationSED, // sets the decimal flag
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OperationRMB, // resets the bit in operand_ implied by operatiopn_
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OperationSMB, // sets the bit in operand_ implied by operatiopn_
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OperationTRB, // sets zero according to operand_ & a, then resets any bits in operand_ that are set in a
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OperationTSB, // sets zero according to operand_ & a, then sets any bits in operand_ that are set in a
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OperationINC, // increments operand_, setting the negative and zero flags
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OperationDEC, // decrements operand_, setting the negative and zero flags
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OperationINX, // increments x, setting the negative and zero flags
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OperationDEX, // decrements x, setting the negative and zero flags
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OperationINY, // increments y, setting the negative and zero flags
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OperationDEY, // decrements y, setting the negative and zero flags
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OperationINA, // increments a, setting the negative and zero flags
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OperationDEA, // decrements a, setting the negative and zero flags
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OperationBPL, // schedules the branch program if the negative flag is clear
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OperationBMI, // schedules the branch program if the negative flag is set
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OperationBVC, // schedules the branch program if the overflow flag is clear
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OperationBVS, // schedules the branch program if the overflow flag is set
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OperationBCC, // schedules the branch program if the carry flag is clear
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OperationBCS, // schedules the branch program if the carry flag is set
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OperationBNE, // schedules the branch program if the zero flag is clear
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OperationBEQ, // schedules the branch program if the zero flag is set
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OperationBRA, // schedules the branch program
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OperationBBRBBS, // inspecting the operation_, if the appropriate bit of operand_ is set or clear schedules a program to read and act upon the second operand; otherwise schedule a program to read and discard it
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OperationTXA, // copies x to a, setting the zero and negative flags
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OperationTYA, // copies y to a, setting the zero and negative flags
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OperationTXS, // copies x to s
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OperationTAY, // copies a to y, setting the zero and negative flags
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OperationTAX, // copies a to x, setting the zero and negative flags
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OperationTSX, // copies s to x, setting the zero and negative flags
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/* The following are amongst the 6502's undocumented (/unintended) operations */
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OperationARR, // performs a mixture of ANDing operand_ into a, and shifting the result right
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OperationSBX, // performs a mixture of an SBC of x&a and operand_, mutating x
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OperationLXA, // loads a and x with (a | 0xee) & operand, setting the negative and zero flags
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OperationANE, // loads a_ with (a | 0xee) & operand & x, setting the negative and zero flags
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OperationANC, // ANDs operand_ into a, setting the negative and zero flags, and loading carry as if the result were shifted right
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OperationLAS, // loads a, x and s with s & operand, setting the negative and zero flags
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CycleFetchFromHalfUpdatedPC, // performs a throwaway read from (PC + (signed)operand).l combined with PC.h
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CycleAddSignedOperandToPC, // sets next_address to PC + (signed)operand. If the high byte of next_address differs from the PC, schedules a throwaway read from the half-updated PC
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OperationAddSignedOperandToPC16, // adds (signed)operand into the PC
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OperationSetFlagsFromOperand, // sets all flags based on operand_
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OperationSetOperandFromFlagsWithBRKSet, // sets operand_ to the value of all flags, with the break flag set
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OperationSetOperandFromFlags, // sets operand_ to the value of all flags
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OperationSetFlagsFromA, // sets the zero and negative flags based on the value of a
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OperationSetFlagsFromX, // sets the zero and negative flags based on the value of x
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OperationSetFlagsFromY, // sets the zero and negative flags based on the value of y
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CycleScheduleJam // schedules the program for operation F2
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};
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using InstructionList = MicroOp[10];
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