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https://github.com/TomHarte/CLK.git
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Slightly wrong as to the details, but gets the controller trying to output.
At an initial look, I think the shift register should end up on the data bus for all odd accesses. Need to investigate more thoroughly.
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@ -84,7 +84,7 @@ void DiskII::select_drive(int drive) {
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void DiskII::set_data_register(uint8_t value) {
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void DiskII::set_data_register(uint8_t value) {
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// printf("Set data register (?)\n");
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// printf("Set data register (?)\n");
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inputs_ |= input_command;
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inputs_ |= input_command;
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// shift_register_ = value;
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shift_register_ = value;
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set_controller_can_sleep();
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set_controller_can_sleep();
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}
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}
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@ -114,6 +114,15 @@ void DiskII::run_for(const Cycles cycles) {
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case 0xa: // shift right, bringing in write protected status
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case 0xa: // shift right, bringing in write protected status
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shift_register_ = (shift_register_ >> 1) | (is_write_protected() ? 0x80 : 0x00);
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shift_register_ = (shift_register_ >> 1) | (is_write_protected() ? 0x80 : 0x00);
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// If the controller is in the sense write protect loop but the register will never change,
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// short circuit further work and return now.
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if(shift_register_ == is_write_protected() ? 0xff : 0x00) {
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if(!drive_is_sleeping_[0]) drives_[0].run_for(Cycles(integer_cycles));
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if(!drive_is_sleeping_[1]) drives_[1].run_for(Cycles(integer_cycles));
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set_controller_can_sleep();
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return;
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}
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break;
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break;
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case 0xb:
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case 0xb:
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// load data register from data bus...
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// load data register from data bus...
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@ -241,7 +250,9 @@ uint8_t DiskII::trigger_address(int address, uint8_t value) {
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case 0xc: return get_shift_register();
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case 0xc: return get_shift_register();
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case 0xd: set_data_register(value); break;
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case 0xd: set_data_register(value); break;
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case 0xe: set_mode(Mode::Read); break;
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case 0xe:
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set_mode(Mode::Read);
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return shift_register_;
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case 0xf: set_mode(Mode::Write); break;
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case 0xf: set_mode(Mode::Write); break;
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}
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}
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return 0xff;
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return 0xff;
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