From 91a6911a51deb2629737609c30b94330ce313a15 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 1 Jun 2022 15:03:03 -0400
Subject: [PATCH] Correct ADDA/SUBA timing.

---
 .../Implementation/68000Mk2Implementation.hpp | 22 ++++++++-----------
 1 file changed, 9 insertions(+), 13 deletions(-)

diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 04d589295..3b4cde002 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -772,19 +772,15 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 
 				Duplicate(SUBAw, ADDAw)	StdCASE(ADDAw, perform_state_ = Perform_np_nn)
 				Duplicate(SUBAl, ADDAl)	StdCASE(ADDAl, {
-					if(instruction_.mode(1) == Mode::AddressRegisterDirect) {
-						perform_state_ = Perform_np_nn;
-					} else {
-						switch(instruction_.mode(0)) {
-							default:
-								perform_state_ = Perform_np_n;
-							break;
-							case Mode::DataRegisterDirect:
-							case Mode::AddressRegisterDirect:
-							case Mode::ImmediateData:
-								perform_state_ = Perform_np_nn;
-							break;
-						}
+					switch(instruction_.mode(0)) {
+						default:
+							perform_state_ = Perform_np_n;
+						break;
+						case Mode::DataRegisterDirect:
+						case Mode::AddressRegisterDirect:
+						case Mode::ImmediateData:
+							perform_state_ = Perform_np_nn;
+						break;
 					}
 				})