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Also 'easy': LSS, LFS, LGS.

Though perhaps I'm off on LES and LDS?
This commit is contained in:
Thomas Harte 2022-03-06 09:28:43 -05:00
parent 49b5889d9e
commit 91a6bf671d

View File

@ -450,22 +450,22 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
// TODO: [0x90, 0x97]: byte set on condition Eb: SETO, SETNO, SETB, SETNB, SETZ, SETNZ, SETBE, SETNBE
// TODO: [0x98, 0x9f]: SETS, SETNS, SETP, SETNP, SETL, SETNL, SETLE, SETNLE
case 0xa0: RequiresMin(i80386); Complete(PUSH, FS, None, data_size_); break;
case 0xa1: RequiresMin(i80386); Complete(POP, FS, None, data_size_); break;
case 0xa0: RequiresMin(i80386); Complete(PUSH, FS, None, data_size_); break;
case 0xa1: RequiresMin(i80386); Complete(POP, FS, None, data_size_); break;
// TODO: 0xa3: BT Ev, Gv
// TODO: 0xa4: SHLD EvGvIb
// TODO: 0xa5: SHLD EvGcCL
case 0xa8: RequiresMin(i80386); Complete(PUSH, GS, None, data_size_); break;
case 0xa9: RequiresMin(i80386); Complete(POP, GS, None, data_size_); break;
case 0xa8: RequiresMin(i80386); Complete(PUSH, GS, None, data_size_); break;
case 0xa9: RequiresMin(i80386); Complete(POP, GS, None, data_size_); break;
// TODO: 0xab: BTS Ev, Gv
// TODO: 0xac: SHRD EvGvIb
// TODO: 0xad: SHRD EvGvCL
// TODO: 0xaf: IMUL Gv, Ev
// TODO: 0xb2: LSS Mp
case 0xb2: RequiresMin(i80386); MemRegReg(LSS, Reg_MemReg, data_size_); break;
// TODO: 0xb3: BTR Ev, Gv
// TODO: 0xb4: LFS Mp
// TODO: 0xb5: LGS Mp
case 0xb4: RequiresMin(i80386); MemRegReg(LFS, Reg_MemReg, data_size_); break;
case 0xb5: RequiresMin(i80386); MemRegReg(LGS, Reg_MemReg, data_size_); break;
// TODO: 0xb6: MOVZX Gv, Eb
// TODO: 0xb7: MOVZX Gv, Ew
// TODO: 0xba: Grp8 Ev, Ib