From 91dc0d5f4a4fc29d7c077aa0e7e06f0eb0977f36 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Mon, 29 May 2017 12:20:33 -0400
Subject: [PATCH] Adjusted HALT to issue never-ending M1 fetches on the next
 instruction.

---
 Processors/Z80/Z80.hpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/Processors/Z80/Z80.hpp b/Processors/Z80/Z80.hpp
index 116d4181a..a6460367b 100644
--- a/Processors/Z80/Z80.hpp
+++ b/Processors/Z80/Z80.hpp
@@ -707,7 +707,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
 					case MicroOp::DecodeOperation:
 						if(current_instruction_page_->increments_r) r_ = (r_ & 0x80) | ((r_ + 1) & 0x7f);
 						pc_.full++;
-						decode_operation(operation_);
+						decode_operation(is_halted_ ? 0x00 : operation_);
 					break;
 
 					case MicroOp::Increment16:			(*(uint16_t *)operation->source)++;											break;
@@ -1385,7 +1385,6 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
 
 					case MicroOp::HALT:
 						is_halted_ = true;
-						pc_.full --;
 					break;
 
 #pragma mark - Internal bookkeeping