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https://github.com/TomHarte/CLK.git
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Makes corrections to ix addressing mode and shift/roll flags.
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@ -182,6 +182,7 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
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case OperationCopyDataToInstruction:
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instruction_buffer_ = data_buffer_;
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data_buffer_.clear();
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continue;
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case OperationCopyAToData:
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@ -672,26 +673,26 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
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case ASL:
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flags_.carry = data_buffer_.value >> (7 + m_shift_);
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data_buffer_.value <<= 1;
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flags_.set_nz(instruction_buffer_.value, m_shift_);
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flags_.set_nz(data_buffer_.value, m_shift_);
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break;
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case LSR:
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flags_.carry = data_buffer_.value & 1;
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data_buffer_.value >>= 1;
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flags_.set_nz(instruction_buffer_.value, m_shift_);
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flags_.set_nz(data_buffer_.value, m_shift_);
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break;
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case ROL:
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data_buffer_.value = (data_buffer_.value << 1) | flags_.carry;
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flags_.carry = data_buffer_.value >> (7 + m_shift_);
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flags_.set_nz(instruction_buffer_.value, m_shift_);
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flags_.set_nz(data_buffer_.value, m_shift_);
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break;
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case ROR: {
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const uint8_t next_carry = data_buffer_.value & 1;
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data_buffer_.value = (data_buffer_.value >> 1) | (flags_.carry << (7 + m_shift_));
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flags_.carry = next_carry;
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flags_.set_nz(instruction_buffer_.value, m_shift_);
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flags_.set_nz(data_buffer_.value, m_shift_);
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} break;
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//
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@ -405,6 +405,12 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CycleFetchPCThrowaway); // IO.
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target(CycleFetchIncrementData); // AAL
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target(CycleFetchData); // AAH
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target(OperationCopyDataToInstruction);
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target(OperationConstructAbsolute);
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read_write(type, is8bit, target);
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}
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