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mirror of https://github.com/TomHarte/CLK.git synced 2024-07-04 18:29:40 +00:00

With correct divider appears to get reset requests posted.

This commit is contained in:
Thomas Harte 2021-02-07 23:05:01 -05:00
parent 77b1efd176
commit 93a80a30d3
3 changed files with 4 additions and 6 deletions

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@ -190,7 +190,7 @@ template<bool is_brk> inline void Executor::perform_interrupt() {
bool log_print = false;
template <Operation operation, AddressingMode addressing_mode> void Executor::perform() {
// log_print |= (program_counter_&0x1fff) == 0x106c;
// log_print |= (program_counter_&0x1fff) == 0x1468;
// log_print &= (program_counter_&0x1fff) != 0x1015;
if((program_counter_&0x1fff) == 0x1f24) {
@ -762,7 +762,7 @@ inline void Executor::subtract_duration(int duration) {
// Update timer 1 and 2 prescaler.
constexpr int t12_divider = 4; // TODO: should be 4, I think.
constexpr int t12_multiplier = 16;
constexpr int t12_multiplier = 1;
timer_divider_ += duration * t12_multiplier;
const int t12_ticks = update_timer(prescalers_[0], timer_divider_ / t12_divider);

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@ -147,7 +147,6 @@ void GLU::run_for(Cycles cycles) {
// MARK: - M50470 port handler
void GLU::set_port_output(int port, uint8_t value) {
ports_[port] = value;
switch(port) {
case 0:
// printf(" {R%d} ", register_address_);
@ -223,10 +222,10 @@ uint8_t GLU::get_port_input(int port) {
return 0x06;
case 2:
// printf("ADB data line input, etc\n");
return ports_[2];
return adb_level_ ? 0x00 : 0x80; // Unclear on this; possibly ADB output is inverted? Or the input is somehow isolated from the output?
case 3:
// printf("ADB data line output, etc\n");
return ports_[3];
return 0x00;
default: assert(false);
}

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@ -50,7 +50,6 @@ class GLU: public InstructionSet::M50740::PortHandler {
uint8_t registers_[16];
uint8_t register_address_;
uint8_t ports_[4];
uint8_t register_latch_ = 0xff;
uint8_t status_ = 0x00;