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Knocks out some transfer operations.
I'm possibly only seven or eight away from being able to test with complete official-opcode-only 6502 code?
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@ -51,7 +51,7 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
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case OperationDecode: {
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// A VERY TEMPORARY piece of logging.
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printf("[%04x] %02x\n", pc_ - 1, instruction_buffer_.value);
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printf("[%04x] %02x\n", pc_ - 2, instruction_buffer_.value); // pc_ - 1 would be correct but this matches a log I made of the 6502.
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active_instruction_ = &instructions[instruction_buffer_.value];
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const auto size_flag = mx_flags_[active_instruction_->size_field];
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@ -306,6 +306,7 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
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case OperationPerform:
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switch(active_instruction_->operation) {
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//
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// Loads, stores and transfers (and NOP).
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//
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@ -330,11 +331,43 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
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direct_ = ((instruction_buffer_.value) & 0xff) << 16;
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break;
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// The below attempts to obey the 8/16-bit mixed transfer rules
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// as documented in https://softpixel.com/~cwright/sianse/docs/65816NFO.HTM
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case TXS:
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// TODO: does this transfer in full when in 8-bit index mode?
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LD(s_, x_.full, x_masks_);
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s_ = x_.full & x_masks_[1];
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break;
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case TSX:
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LD(x_, s_.full, x_masks_);
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break;
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case TXY:
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LD(x_, y_.full, x_masks_);
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break;
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case TYX:
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LD(y_, x_.full, x_masks_);
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break;
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case TAX:
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LD(x_, a_.full, x_masks_);
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break;
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case TAY:
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LD(x_, a_.full, x_masks_);
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break;
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case TXA:
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LD(a_, x_.full, m_masks_);
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break;
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case TYA:
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LD(a_, y_.full, m_masks_);
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break;
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case STA:
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data_buffer_.value = a_.full & m_masks_[1];
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data_buffer_.size = 2 - m_flag();
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@ -558,11 +591,11 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
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// PHP, PHD, PHK,
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// TRB, TSB,
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// REP, SEP,
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// TAX, TAY, TCD, TCS, TDC, TSC, TSX, TXA, TXS, TXY, TYA, TYX,
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// XCE, XBA,
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// STP, WAI,
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// RTI, RTL,
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// BRK,
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// TCD, TCS, TDC, TSC
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default:
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assert(false);
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