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synced 2024-11-22 12:33:29 +00:00
Add just enough to persuade self that execution is broadly sane.
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commit
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@ -24,22 +24,29 @@ struct Memory {
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(void)source;
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(void)source;
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(void)mode;
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(void)mode;
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(void)trans;
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(void)trans;
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printf("W of %08x to %08x [%lu]\n", source, address, sizeof(IntT));
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return true;
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return true;
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}
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}
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template <typename IntT>
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template <typename IntT>
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bool read(uint32_t address, IntT &source, Mode mode, bool trans) {
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bool read(uint32_t address, IntT &source, Mode mode, bool trans) {
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if(address > 0x3800000) {
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if(address > 0x3800000) {
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has_moved_rom_ = true;
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source = *reinterpret_cast<const IntT *>(&rom[address - 0x3800000]);
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source = *reinterpret_cast<const IntT *>(&rom[address - 0x3800000]);
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} else {
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} else if(!has_moved_rom_) {
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// TODO: this is true only very transiently.
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// TODO: this is true only very transiently.
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source = *reinterpret_cast<const IntT *>(&rom[address]);
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source = *reinterpret_cast<const IntT *>(&rom[address]);
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} else {
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printf("Unknown read from %08x [%lu]\n", address, sizeof(IntT));
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}
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}
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(void)mode;
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(void)mode;
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(void)trans;
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(void)trans;
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return true;
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return true;
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}
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}
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private:
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bool has_moved_rom_ = false;
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};
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};
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}
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}
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@ -194,6 +201,9 @@ struct Memory {
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XCTAssertEqual(carry, 0);
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XCTAssertEqual(carry, 0);
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}
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}
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/*
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TODO: turn the below into a trace-driven test case.
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- (void)testROM319 {
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- (void)testROM319 {
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constexpr ROM::Name rom_name = ROM::Name::AcornRISCOS319;
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constexpr ROM::Name rom_name = ROM::Name::AcornRISCOS319;
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ROM::Request request(rom_name);
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ROM::Request request(rom_name);
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@ -203,13 +213,13 @@ struct Memory {
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executor.bus_.rom = roms.find(rom_name)->second;
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executor.bus_.rom = roms.find(rom_name)->second;
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uint32_t pc = 0;
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uint32_t pc = 0;
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for(int c = 0; c < 200; c++) {
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for(int c = 0; c < 1000; c++) {
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uint32_t instruction;
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uint32_t instruction;
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executor.bus_.read(pc, instruction, executor.mode(), false);
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executor.bus_.read(pc, instruction, executor.mode(), false);
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printf("%08x: %08x\n", pc, instruction);
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printf("%08x: %08x\n", pc, instruction);
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dispatch<Model::ARMv2>(pc, instruction, executor);
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dispatch<Model::ARMv2>(pc, instruction, executor);
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}
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}
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}
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}*/
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@end
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@end
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