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https://github.com/TomHarte/CLK.git
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Attempt a real slot-by-slot blit.
This commit is contained in:
Thomas Harte
parent
5d992758f8
commit
94a90b7a89
@ -223,8 +223,9 @@ uint16_t Blitter::get_status() {
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bool Blitter::advance_dma() {
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bool Blitter::advance_dma() {
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if(!height_) return false;
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if(!height_) return false;
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not_zero_flag_ = false;
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if(line_mode_) {
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if(line_mode_) {
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not_zero_flag_ = false;
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// As-yet unimplemented:
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// As-yet unimplemented:
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assert(b_data_ == 0xffff);
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assert(b_data_ == 0xffff);
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@ -332,139 +333,140 @@ bool Blitter::advance_dma() {
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draw_ = true;
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draw_ = true;
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}
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}
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}
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}
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busy_ = false;
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} else {
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} else {
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// Copy mode.
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// Copy mode.
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if(!busy_) {
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sequencer_.begin();
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a32_ = 0;
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b32_ = 0;
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// Quick hack: do the entire action atomically.
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y_ = 0;
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sequencer_.begin();
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x_ = 0;
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a32_ = 0;
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loop_index_ = -1;
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b32_ = 0;
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write_phase_ = WritePhase::Starting;
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not_zero_flag_ = 0;
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busy_ = true;
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}
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y_ = 0;
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const auto next = sequencer_.next();
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x_ = 0;
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int loop_index_ = -1;
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write_phase_ = WritePhase::Starting;
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while(true) {
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// If this is the start of a new iteration, check for end of line,
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const auto next = sequencer_.next();
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// or of blit, and pick an appropriate mask for A based on location.
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if(next.second != loop_index_) {
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transient_a_mask_ = x_ ? 0xffff : a_mask_[0];
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// If this is the start of a new iteration, check for end of line,
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// Check whether a complete row was completed in the previous iteration.
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// or of blit, and pick an appropriate mask for A based on location.
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// If so then add modulos.
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if(next.second != loop_index_) {
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if(!x_ && y_) {
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transient_a_mask_ = x_ ? 0xffff : a_mask_[0];
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pointer_[0] += modulos_[0] * channel_enables_[0] * direction_;
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pointer_[1] += modulos_[1] * channel_enables_[1] * direction_;
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pointer_[2] += modulos_[2] * channel_enables_[2] * direction_;
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pointer_[3] += modulos_[3] * channel_enables_[3] * direction_;
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}
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// Check whether a complete row was completed in the previous iteration.
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++x_;
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// If so then add modulos.
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if(x_ == width_) {
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if(!x_ && y_) {
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transient_a_mask_ &= a_mask_[1];
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pointer_[0] += modulos_[0] * channel_enables_[0] * direction_;
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x_ = 0;
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pointer_[1] += modulos_[1] * channel_enables_[1] * direction_;
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++y_;
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pointer_[2] += modulos_[2] * channel_enables_[2] * direction_;
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if(y_ == height_) {
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pointer_[3] += modulos_[3] * channel_enables_[3] * direction_;
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sequencer_.complete();
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}
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}
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++x_;
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if(x_ == width_) {
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transient_a_mask_ &= a_mask_[1];
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x_ = 0;
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++y_;
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if(y_ == height_) {
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sequencer_.complete();
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}
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}
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++loop_index_;
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}
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}
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++loop_index_;
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}
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using Channel = BlitterSequencer::Channel;
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using Channel = BlitterSequencer::Channel;
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switch(next.first) {
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switch(next.first) {
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case Channel::A:
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case Channel::A:
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a_data_ = ram_[pointer_[0] & ram_mask_];
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a_data_ = ram_[pointer_[0] & ram_mask_];
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pointer_[0] += direction_;
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pointer_[0] += direction_;
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continue;
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return true;
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case Channel::B:
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case Channel::B:
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b_data_ = ram_[pointer_[1] & ram_mask_];
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b_data_ = ram_[pointer_[1] & ram_mask_];
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pointer_[1] += direction_;
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pointer_[1] += direction_;
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continue;
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return true;
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case Channel::C:
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case Channel::C:
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c_data_ = ram_[pointer_[2] & ram_mask_];
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c_data_ = ram_[pointer_[2] & ram_mask_];
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pointer_[2] += direction_;
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pointer_[2] += direction_;
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continue;
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return true;
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case Channel::None:
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case Channel::None:
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continue;
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return false;
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case Channel::Write: break;
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case Channel::Write: break;
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case Channel::FlushPipeline:
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case Channel::FlushPipeline:
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// HACK. REMOVE ONCE NON-BLOCKING.
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posit_interrupt(InterruptFlag::Blitter);
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posit_interrupt(InterruptFlag::Blitter);
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height_ = 0;
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height_ = 0;
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busy_ = false;
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// END HACK.
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if(write_phase_ == WritePhase::Full) {
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if(write_phase_ == WritePhase::Full) {
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ram_[write_address_ & ram_mask_] = write_value_;
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}
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return true;
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}
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a32_ = (a32_ << 16) | (a_data_ & transient_a_mask_);
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b32_ = (b32_ << 16) | b_data_;
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uint16_t a, b;
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// The barrel shifter shifts to the right in ascending address mode,
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// but to the left otherwise.
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if(!one_dot_) {
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a = uint16_t(a32_ >> shifts_[0]);
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b = uint16_t(b32_ >> shifts_[1]);
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} else {
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// TODO: there must be a neater solution than this.
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a = uint16_t(
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(a32_ << shifts_[0]) |
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(a32_ >> (32 - shifts_[0]))
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);
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b = uint16_t(
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(b32_ << shifts_[1]) |
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(b32_ >> (32 - shifts_[1]))
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);
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}
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uint16_t output =
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apply_minterm<uint16_t>(
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a,
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b,
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c_data_,
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minterms_);
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if(exclusive_fill_ || inclusive_fill_) {
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// Use the fill tables nibble-by-nibble to figure out the filled word.
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uint16_t fill_output = 0;
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int ongoing_carry = fill_carry_;
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const int type_mask = exclusive_fill_ ? (1 << 5) : 0;
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for(int c = 0; c < 16; c += 4) {
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const int total_index = (output & 0xf) | (ongoing_carry << 4) | type_mask;
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fill_output |= ((fill_values[total_index >> 3] >> ((total_index & 7) * 4)) & 0xf) << c;
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ongoing_carry = (fill_carries[total_index >> 5] >> (total_index & 31)) & 1;
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output >>= 4;
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}
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output = fill_output;
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fill_carry_ = ongoing_carry;
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}
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not_zero_flag_ |= output;
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switch(write_phase_) {
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case WritePhase::Full:
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ram_[write_address_ & ram_mask_] = write_value_;
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ram_[write_address_ & ram_mask_] = write_value_;
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[[fallthrough]];
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}
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return true;
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}
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case WritePhase::Starting:
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a32_ = (a32_ << 16) | (a_data_ & transient_a_mask_);
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write_phase_ = WritePhase::Full;
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b32_ = (b32_ << 16) | b_data_;
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write_address_ = pointer_[3];
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write_value_ = output;
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pointer_[3] += direction_;
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continue;
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default: break;
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uint16_t a, b;
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// The barrel shifter shifts to the right in ascending address mode,
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// but to the left otherwise.
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if(!one_dot_) {
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a = uint16_t(a32_ >> shifts_[0]);
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b = uint16_t(b32_ >> shifts_[1]);
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} else {
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// TODO: there must be a neater solution than this.
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a = uint16_t(
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(a32_ << shifts_[0]) |
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(a32_ >> (32 - shifts_[0]))
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);
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b = uint16_t(
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(b32_ << shifts_[1]) |
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(b32_ >> (32 - shifts_[1]))
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);
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}
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uint16_t output =
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apply_minterm<uint16_t>(
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a,
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b,
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c_data_,
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minterms_);
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if(exclusive_fill_ || inclusive_fill_) {
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// Use the fill tables nibble-by-nibble to figure out the filled word.
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uint16_t fill_output = 0;
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int ongoing_carry = fill_carry_;
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const int type_mask = exclusive_fill_ ? (1 << 5) : 0;
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for(int c = 0; c < 16; c += 4) {
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const int total_index = (output & 0xf) | (ongoing_carry << 4) | type_mask;
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fill_output |= ((fill_values[total_index >> 3] >> ((total_index & 7) * 4)) & 0xf) << c;
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ongoing_carry = (fill_carries[total_index >> 5] >> (total_index & 31)) & 1;
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output >>= 4;
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}
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}
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output = fill_output;
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fill_carry_ = ongoing_carry;
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}
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not_zero_flag_ |= output;
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switch(write_phase_) {
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case WritePhase::Full:
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ram_[write_address_ & ram_mask_] = write_value_;
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[[fallthrough]];
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case WritePhase::Starting:
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write_phase_ = WritePhase::Full;
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write_address_ = pointer_[3];
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write_value_ = output;
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pointer_[3] += direction_;
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return true;
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default: assert(false);
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}
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}
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}
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}
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@ -215,6 +215,8 @@ class Blitter: public DMADevice<4, 4> {
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} write_phase_;
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} write_phase_;
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int y_, x_;
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int y_, x_;
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uint16_t transient_a_mask_;
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uint16_t transient_a_mask_;
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bool busy_ = false;
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int loop_index_ = -1;
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};
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};
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}
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}
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