From 960b289e708aac7e270147dfc4b3e359bb8da60e Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 15 Sep 2019 15:03:06 -0400
Subject: [PATCH] Edges closer towards proper DMA operation.

Specifically: differentiates the three kinds of DMA operation. Still doesn't act correctly with regard to DACK though, and leaves the bus instantaneously improperly formed. Which I'm tempted to try to fix on the target side by properly obeying delays.
---
 Components/5380/ncr5380.cpp | 13 ++++++++++++-
 Components/5380/ncr5380.hpp |  5 +++--
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/Components/5380/ncr5380.cpp b/Components/5380/ncr5380.cpp
index 43f898c44..1a21f0758 100644
--- a/Components/5380/ncr5380.cpp
+++ b/Components/5380/ncr5380.cpp
@@ -25,6 +25,14 @@ void NCR5380::write(int address, uint8_t value, bool dma_acknowledge) {
 		case 0:
 			LOG("[SCSI 0] Set current SCSI bus state to " << PADHEX(2) << int(value));
 			data_bus_ = value;
+
+			if(dma_request_ && dma_operation_ == DMAOperation::Send) {
+				printf("w %02x\n", value);
+				dma_acknowledge_ = true;
+				dma_request_ = false;
+				update_control_output();
+				bus_.set_device_output(device_id_, bus_output_);
+			}
 		break;
 
 		case 1: {
@@ -89,14 +97,17 @@ void NCR5380::write(int address, uint8_t value, bool dma_acknowledge) {
 
 		case 5:
 			LOG("[SCSI 5] Start DMA send: " << PADHEX(2) << int(value));
+			dma_operation_ = DMAOperation::Send;
 		break;
 
 		case 6:
 			LOG("[SCSI 6] Start DMA target receive: " << PADHEX(2) << int(value));
+			dma_operation_ = DMAOperation::TargetReceive;
 		break;
 
 		case 7:
 			LOG("[SCSI 7] Start DMA initiator receive: " << PADHEX(2) << int(value));
+			dma_operation_ = DMAOperation::InitiatorReceive;
 		break;
 	}
 
@@ -121,7 +132,7 @@ uint8_t NCR5380::read(int address, bool dma_acknowledge) {
 		case 0:
 			LOG("[SCSI 0] Get current SCSI bus state: " << PADHEX(2) << (bus_.get_state() & 0xff));
 
-			if(dma_request_ && state_ == ExecutionState::PerformingDMA) {
+			if(dma_request_ && dma_operation_ == DMAOperation::InitiatorReceive) {
 				dma_acknowledge_ = true;
 				dma_request_ = false;
 				update_control_output();
diff --git a/Components/5380/ncr5380.hpp b/Components/5380/ncr5380.hpp
index 2bda86715..2842dfdf1 100644
--- a/Components/5380/ncr5380.hpp
+++ b/Components/5380/ncr5380.hpp
@@ -76,8 +76,9 @@ class NCR5380 final: public ClockingHint::Source {
 		} state_ = ExecutionState::None;
 		enum class DMAOperation {
 			Ready,
-			Reading,
-			Writing
+			Send,
+			TargetReceive,
+			InitiatorReceive
 		} dma_operation_ = DMAOperation::Ready;
 		int time_in_state_ = 0;
 		bool lost_arbitration_ = false, arbitration_in_progress_ = false;