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Merge pull request #100 from TomHarte/SuperChipDetection
Adds detection and emulation of the Super Chip
This commit is contained in:
Thomas Harte
GitHub
commit
997707a45b
@ -87,8 +87,21 @@ unsigned int Machine::perform_bus_operation(CPU6502::BusOperation operation, uin
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}
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// check for a ROM read
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if((address&0x1000) && isReadOperation(operation)) {
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returnValue &= rom_pages_[(address >> 10)&3][address&1023];
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uint16_t masked_address = address & 0x1fff;
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if(address&0x1000)
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{
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if(isReadOperation(operation) && (!uses_superchip_ || masked_address > 0x10ff)) {
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returnValue &= rom_pages_[(address >> 10)&3][address&1023];
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}
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// check for a Super Chip RAM access
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if(uses_superchip_ && masked_address < 0x1100) {
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if(masked_address < 0x1080) {
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superchip_ram_[masked_address & 0x7f] = *value;
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} else {
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returnValue &= superchip_ram_[masked_address & 0x7f];
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}
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}
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}
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// check for a RAM access
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@ -263,6 +276,8 @@ void Machine::configure_as_target(const StaticAnalyser::Target &target)
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rom_pages_[1] = &rom_[1024 & romMask];
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rom_pages_[2] = &rom_[2048 & romMask];
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rom_pages_[3] = &rom_[3072 & romMask];
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uses_superchip_ = target.atari.uses_superchip;
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}
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#pragma mark - Audio and Video
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@ -56,9 +56,14 @@ class Machine:
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virtual void crt_did_end_batch_of_frames(Outputs::CRT::CRT *crt, unsigned int number_of_frames, unsigned int number_of_unexpected_vertical_syncs);
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private:
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// ROM information
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uint8_t *rom_, *rom_pages_[4];
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size_t rom_size_;
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// cartridge RAM expansion store
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uint8_t superchip_ram_[128];
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bool uses_superchip_;
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// the RIOT and TIA
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PIA mos6532_;
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std::unique_ptr<TIA> tia_;
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@ -27,9 +27,10 @@ void StaticAnalyser::Atari::AddTargets(
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target.tapes = tapes;
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target.cartridges = cartridges;
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target.atari.paging_model = Atari2600PagingModel::None;
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target.atari.uses_superchip = false;
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// try to figure out the paging scheme
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/* if(!cartridges.empty())
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if(!cartridges.empty())
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{
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const std::list<Storage::Cartridge::Cartridge::Segment> &segments = cartridges.front()->get_segments();
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if(segments.size() == 1)
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@ -48,9 +49,23 @@ void StaticAnalyser::Atari::AddTargets(
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}
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StaticAnalyser::MOS6502::Disassembly disassembly =
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StaticAnalyser::MOS6502::Disassemble(segment.data, 0x1000, {entry_address, break_address}, 0x1fff);
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printf("%p", &disassembly);
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// check for any sort of on-cartridge RAM; that might imply a Super Chip or else immediately tip the
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// hat that this is a CBS RAM+ cartridge
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if(!disassembly.internal_stores.empty())
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{
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bool writes_above_128 = false;
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for(uint16_t address : disassembly.internal_stores)
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{
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writes_above_128 |= ((address & 0x1fff) > 0x10ff) && ((address & 0x1fff) < 0x1200);
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}
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if(writes_above_128)
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target.atari.paging_model = Atari2600PagingModel::CBSRamPlus;
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else
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target.atari.uses_superchip = true;
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}
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}
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}*/
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}
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destination.push_back(target);
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}
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@ -189,7 +189,7 @@ static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<
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break;
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case 0x87: case 0x97: case 0x83: case 0x8f:
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instruction.operation = Instruction::SAX;
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instruction.operation = Instruction::AXS;
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break;
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case 0xa7: case 0xb7: case 0xa3: case 0xb3: case 0xaf: case 0xbf:
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instruction.operation = Instruction::LAX;
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@ -205,7 +205,7 @@ static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<
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IM_INSTRUCTION(0x6b, Instruction::ARR)
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IM_INSTRUCTION(0x8b, Instruction::XAA)
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IM_INSTRUCTION(0xab, Instruction::LAX)
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IM_INSTRUCTION(0xcb, Instruction::AXS)
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IM_INSTRUCTION(0xcb, Instruction::SAX)
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IM_INSTRUCTION(0xeb, Instruction::SBC)
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case 0x93: case 0x9f:
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instruction.operation = Instruction::AHX;
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@ -259,16 +259,36 @@ static void AddToDisassembly(PartialDisassembly &disassembly, const std::vector<
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disassembly.disassembly.instructions_by_address[instruction.address] = instruction;
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// TODO: something wider-ranging than this
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if((instruction.addressing_mode == Instruction::Absolute || instruction.addressing_mode == Instruction::ZeroPage) && (instruction.operand < start_address || instruction.operand >= start_address + memory.size()))
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if(instruction.addressing_mode == Instruction::Absolute || instruction.addressing_mode == Instruction::ZeroPage)
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{
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if( instruction.operation == Instruction::STY ||
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instruction.operation == Instruction::STX ||
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instruction.operation == Instruction::STA)
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disassembly.disassembly.external_stores.insert(instruction.operand);
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if( instruction.operation == Instruction::LDY ||
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instruction.operation == Instruction::LDX ||
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instruction.operation == Instruction::LDA)
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disassembly.disassembly.external_loads.insert(instruction.operand);
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bool is_external = (instruction.operand&address_mask) < start_address || (instruction.operand&address_mask) >= start_address + memory.size();
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switch(instruction.operation)
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{
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default: break;
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case Instruction::LDY: case Instruction::LDX: case Instruction::LDA:
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case Instruction::LAX:
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case Instruction::AND: case Instruction::EOR: case Instruction::ORA: case Instruction::BIT:
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case Instruction::ADC: case Instruction::SBC:
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case Instruction::LAS:
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case Instruction::CMP: case Instruction::CPX: case Instruction::CPY:
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(is_external ? disassembly.disassembly.external_loads : disassembly.disassembly.internal_loads).insert(instruction.operand);
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break;
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case Instruction::STY: case Instruction::STX: case Instruction::STA:
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case Instruction::AXS: case Instruction::AHX: case Instruction::SHX: case Instruction::SHY:
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case Instruction::TAS:
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(is_external ? disassembly.disassembly.external_stores : disassembly.disassembly.internal_stores).insert(instruction.operand);
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break;
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case Instruction::SLO: case Instruction::RLA: case Instruction::SRE: case Instruction::RRA:
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case Instruction::DCP: case Instruction::ISC:
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case Instruction::INC: case Instruction::DEC:
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case Instruction::ASL: case Instruction::ROL: case Instruction::LSR: case Instruction::ROR:
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(is_external ? disassembly.disassembly.external_modifies : disassembly.disassembly.internal_modifies).insert(instruction.operand);
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break;
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}
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}
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// decide on overall flow control
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@ -65,6 +65,7 @@ struct Disassembly {
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std::map<uint16_t, Instruction> instructions_by_address;
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std::set<uint16_t> outward_calls;
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std::set<uint16_t> external_stores, external_loads, external_modifies;
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std::set<uint16_t> internal_stores, internal_loads, internal_modifies;
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};
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Disassembly Disassemble(const std::vector<uint8_t> &memory, uint16_t start_address, std::vector<uint16_t> entry_points, uint16_t address_mask = 0xffff);
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@ -32,7 +32,8 @@ enum class Atari2600PagingModel {
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Atari32k,
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ActivisionStack,
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ParkerBros,
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Tigervision
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Tigervision,
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CBSRamPlus
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};
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/*!
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@ -57,6 +58,7 @@ struct Target {
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struct {
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Atari2600PagingModel paging_model;
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bool uses_superchip;
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} atari;
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struct {
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