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Add quick clock-rate notes.
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@ -15,6 +15,26 @@
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using namespace TI::TMS;
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//
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// TODO notes.
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//
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// The TMS and Master System VDP run at 342 cycles/line.
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//
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// The Mega Drive VDP has 3420 master clocks per line, which it divides
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// by 4 or 5 depending on pixel rate and which part of a line is active.
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// (And, presumably, by 10 if operating in Master System mode?)
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// Cf. https://gendev.spritesmind.net/forum/viewtopic.php?t=851 etc.
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//
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// The MSX2+ Yamaha VDPs have 1368 cycles/line.
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//
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// So if clock scaling were common, it would need to be to:
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//
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// 3420 = 2 * 2 * 3 * 3 * 5 * 19
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// 1368 = 2 * 2 * 2 * 3 * 3 * 19
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//
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// => 2^3 * 3^2 * 5 * 19 = 6840
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// ... which
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namespace {
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constexpr uint8_t StatusInterrupt = 0x80;
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