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Attempts direct and direct indexed indirect.

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This commit is contained in:
Thomas Harte 2020-10-04 22:06:25 -04:00
parent d8dccf2500
commit 9a05c68ce7
1 changed files with 26 additions and 7 deletions
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33
Processors/65816/Implementation/65816Implementation.hpp
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@ -21,6 +21,9 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
#define read(address, value) perform_bus(address, value, MOS6502Esque::Read)
#define write(address, value) perform_bus(address, value, MOS6502Esque::Write)
#define x() (x_.full & x_masks_[1])
#define y() (y_.full & x_masks_[1])
Cycles number_of_cycles = cycles + cycles_left_to_run_;
while(number_of_cycles > Cycles(0)) {
const MicroOp operation = *next_op_;
@ -107,15 +110,15 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
break;
case CycleFetchBlockX:
read(((instruction_buffer_.value & 0xff00) << 8) | (x_.full & x_masks_[1]), data_buffer_.any_byte());
read(((instruction_buffer_.value & 0xff00) << 8) | x(), data_buffer_.any_byte());
break;
case CycleFetchBlockY:
read(((instruction_buffer_.value & 0xff00) << 8) | (y_.full & x_masks_[1]), &throwaway);
read(((instruction_buffer_.value & 0xff00) << 8) | y(), &throwaway);
break;
case CycleStoreBlockY:
write(((instruction_buffer_.value & 0xff00) << 8) | (y_.full & x_masks_[1]), data_buffer_.any_byte());
write(((instruction_buffer_.value & 0xff00) << 8) | x(), data_buffer_.any_byte());
break;
#undef increment_data_address
@ -172,16 +175,16 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
break;
case OperationConstructAbsoluteIndexedIndirect:
data_address_ = (instruction_buffer_.value + (x_.full & x_masks_[1])) & 0xffff;
data_address_ = (instruction_buffer_.value + x()) & 0xffff;
break;
case OperationConstructAbsoluteLongX:
data_address_ = instruction_buffer_.value + (x_.full & x_masks_[1]);
data_address_ = instruction_buffer_.value + x();
break;
case OperationConstructAbsoluteXRead:
case OperationConstructAbsoluteX:
data_address_ = ((instruction_buffer_.value + (x_.full & x_masks_[1])) & 0xffff) | data_bank_;
data_address_ = ((instruction_buffer_.value + x()) & 0xffff) | data_bank_;
incorrect_data_address_ = (data_address_ & 0xff) | (instruction_buffer_.value & 0xff00) | data_bank_;
// If the incorrect address isn't actually incorrect, skip its usage.
@ -192,7 +195,7 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
case OperationConstructAbsoluteYRead:
case OperationConstructAbsoluteY:
data_address_ = ((instruction_buffer_.value + (y_.full & x_masks_[1])) & 0xffff) | data_bank_;
data_address_ = ((instruction_buffer_.value + y()) & 0xffff) | data_bank_;
incorrect_data_address_ = (data_address_ & 0xff) | (instruction_buffer_.value & 0xff00) | data_bank_;
// If the incorrect address isn't actually incorrect, skip its usage.
@ -201,6 +204,20 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
}
break;
case OperationConstructDirect:
data_address_ = direct_ + instruction_buffer_.value;
if(!(direct_&0xff)) {
++next_op_;
}
break;
case OperationConstructDirectIndexedIndirect:
data_address_ = direct_ + x() + instruction_buffer_.value;
if(!(direct_&0xff)) {
++next_op_;
}
break;
//
// Performance.
//
@ -301,6 +318,8 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
#undef read
#undef write
#undef bus_operation
#undef x
#undef y
cycles_left_to_run_ = number_of_cycles;
}