From 9acc80260f00853a8af6eed677786662eb42b97d Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Wed, 9 Oct 2024 11:59:27 -0400 Subject: [PATCH] Eliminate phases due to lack of evidence. --- Components/6845/CRTC6845.hpp | 32 +++--------------------------- Machines/AmstradCPC/AmstradCPC.cpp | 8 +------- Machines/PCCompatible/CGA.hpp | 3 +-- Machines/PCCompatible/MDA.hpp | 3 +-- 4 files changed, 6 insertions(+), 40 deletions(-) diff --git a/Components/6845/CRTC6845.hpp b/Components/6845/CRTC6845.hpp index 6fb685c7a..b3710027d 100644 --- a/Components/6845/CRTC6845.hpp +++ b/Components/6845/CRTC6845.hpp @@ -30,19 +30,7 @@ struct BusState { class BusHandler { public: - /*! - Performs the first phase of a 6845 bus cycle; this is the phase in which it is intended that - systems using the 6845 respect the bus state and produce pixels, sync or whatever they require. - */ - void perform_bus_cycle_phase1(const BusState &) {} - - /*! - Performs the second phase of a 6845 bus cycle. Some bus state, including sync, is updated - directly after phase 1 and hence is visible to an observer during phase 2. Handlers may therefore - implement @c perform_bus_cycle_phase2 to be notified of the availability of that state without - having to wait until the next cycle has begun. - */ - void perform_bus_cycle_phase2(const BusState &) {} + void perform_bus_cycle(const BusState &) {} }; enum class Personality { @@ -196,10 +184,7 @@ template cl bus_state_.cursor = is_cursor_line_ && bus_state_.refresh_address == layout_.cursor_address; bus_state_.display_enable = character_is_visible_ && line_is_visible_; - - // TODO: considate the two below. - perform_bus_cycle_phase1(); - perform_bus_cycle_phase2(); + bus_handler_.perform_bus_cycle(bus_state_); // // Shared, stateless signals. @@ -212,7 +197,7 @@ template cl character_total_hit && was_eof && ( layout_.interlace_mode_ == InterlaceMode::Off || - !(bus_state_.field_count&1) + !odd_field_ ); // @@ -373,17 +358,6 @@ template cl private: static constexpr uint16_t RefreshMask = (personality >= Personality::EGA) ? 0xffff : 0x3fff; - inline void perform_bus_cycle_phase1() { - // Skew theory of operation: keep a history of the last three states, and apply whichever is selected. -// character_is_visible_shifter_ = (character_is_visible_shifter_ << 1) | unsigned(character_is_visible_); -// bus_state_.display_enable = (int(character_is_visible_shifter_) & display_skew_mask_) && line_is_visible_; - bus_handler_.perform_bus_cycle_phase1(bus_state_); - } - - inline void perform_bus_cycle_phase2() { - bus_handler_.perform_bus_cycle_phase2(bus_state_); - } - BusHandlerT &bus_handler_; BusState bus_state_; diff --git a/Machines/AmstradCPC/AmstradCPC.cpp b/Machines/AmstradCPC/AmstradCPC.cpp index a74f57120..58685125f 100644 --- a/Machines/AmstradCPC/AmstradCPC.cpp +++ b/Machines/AmstradCPC/AmstradCPC.cpp @@ -189,7 +189,7 @@ class CRTCBusHandler { The CRTC entry function for the main part of each clock cycle; takes the current bus state and determines what output to produce based on the current palette and mode. */ - forceinline void perform_bus_cycle_phase1(const Motorola::CRTC::BusState &state) { + forceinline void perform_bus_cycle(const Motorola::CRTC::BusState &state) { // The gate array waits 2us to react to the CRTC's vsync signal, and then // caps output at 4us. Since the clock rate is 1Mhz, that's 2 and 4 cycles, // respectively. @@ -299,13 +299,7 @@ class CRTCBusHandler { } } } - } - /*! - The CRTC entry function for phase 2 of each bus cycle, in which the next sync line state becomes - visible early. The CPC uses changes in sync to clock the interrupt timer. - */ - void perform_bus_cycle_phase2(const Motorola::CRTC::BusState &state) { // Notify a leading hsync edge to the interrupt timer. // Per Interrupts in the CPC: "to be confirmed: does gate array count positive or negative edge transitions of HSYNC signal?"; // if you take it as given that display mode is latched as a result of hsync then Pipe Mania seems to imply that the count diff --git a/Machines/PCCompatible/CGA.hpp b/Machines/PCCompatible/CGA.hpp index 7dafe2205..b3818c882 100644 --- a/Machines/PCCompatible/CGA.hpp +++ b/Machines/PCCompatible/CGA.hpp @@ -173,7 +173,7 @@ class CGA { return new_state; } - void perform_bus_cycle_phase1(const Motorola::CRTC::BusState &state) { + void perform_bus_cycle(const Motorola::CRTC::BusState &state) { // Determine new output state. update_hsync(state.hsync); const OutputState new_state = implied_state(state); @@ -246,7 +246,6 @@ class CGA { count = 0; } } - void perform_bus_cycle_phase2(const Motorola::CRTC::BusState &) {} void flush_pixels() { crt.output_data(count * active_clock_divider, size_t((count * active_pixels_per_tick) / 8)); diff --git a/Machines/PCCompatible/MDA.hpp b/Machines/PCCompatible/MDA.hpp index d38b7f924..dc0a79c42 100644 --- a/Machines/PCCompatible/MDA.hpp +++ b/Machines/PCCompatible/MDA.hpp @@ -104,7 +104,7 @@ class MDA { return control_; } - void perform_bus_cycle_phase1(const Motorola::CRTC::BusState &state) { + void perform_bus_cycle(const Motorola::CRTC::BusState &state) { // Determine new output state. const OutputState new_state = (state.hsync | state.vsync) ? OutputState::Sync : @@ -207,7 +207,6 @@ class MDA { pixels = pixel_pointer = nullptr; } } - void perform_bus_cycle_phase2(const Motorola::CRTC::BusState &) {} Outputs::CRT::CRT crt;