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https://github.com/TomHarte/CLK.git
synced 2024-12-27 16:31:31 +00:00
Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures.
This commit is contained in:
Thomas Harte
parent
ab8a98f1df
commit
9bc2b48d9b
@ -57,19 +57,19 @@ fileprivate struct RegisterState {
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de = UInt16(dictionary["de"] as! NSNumber)
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hl = UInt16(dictionary["hl"] as! NSNumber)
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afDash = UInt16((dictionary["afDash"] as! NSNumber).int32Value)
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bcDash = UInt16((dictionary["bcDash"] as! NSNumber).int32Value)
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deDash = UInt16((dictionary["deDash"] as! NSNumber).int32Value)
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hlDash = UInt16((dictionary["hlDash"] as! NSNumber).int32Value)
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afDash = UInt16(dictionary["afDash"] as! NSNumber)
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bcDash = UInt16(dictionary["bcDash"] as! NSNumber)
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deDash = UInt16(dictionary["deDash"] as! NSNumber)
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hlDash = UInt16(dictionary["hlDash"] as! NSNumber)
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ix = UInt16((dictionary["ix"] as! NSNumber).int32Value)
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iy = UInt16((dictionary["iy"] as! NSNumber).int32Value)
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ix = UInt16(dictionary["ix"] as! NSNumber)
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iy = UInt16(dictionary["iy"] as! NSNumber)
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sp = UInt16((dictionary["sp"] as! NSNumber).int32Value)
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pc = UInt16((dictionary["pc"] as! NSNumber).int32Value)
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sp = UInt16(dictionary["sp"] as! NSNumber)
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pc = UInt16(dictionary["pc"] as! NSNumber)
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i = UInt8((dictionary["i"] as! NSNumber).int32Value)
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r = UInt8((dictionary["r"] as! NSNumber).int32Value)
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i = UInt8(dictionary["i"] as! NSNumber)
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r = UInt8(dictionary["r"] as! NSNumber)
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iff1 = (dictionary["iff1"] as! NSNumber).boolValue
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iff2 = (dictionary["iff2"] as! NSNumber).boolValue
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@ -151,10 +151,17 @@ class FUSETests: XCTestCase {
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XCTAssert(inputArray != nil && outputArray != nil)
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var index = 0
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var failures = 0
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// var failures = 0
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for item in inputArray {
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let itemDictionary = item as! [String: Any]
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let outputDictionary = outputArray[index] as! [String: Any]
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index = index + 1
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let name = itemDictionary["name"] as! String
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// if name != "fd86" {
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// continue
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// }
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let initialState = RegisterState(dictionary: itemDictionary["state"] as! [String: Any])
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let targetState = RegisterState(dictionary: outputDictionary["state"] as! [String: Any])
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@ -175,22 +182,20 @@ class FUSETests: XCTestCase {
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}
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}
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machine.runForNumber(ofCycles: Int32(initialState.tStates))
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machine.runToNextInstruction()
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machine.runForNumber(ofCycles: Int32(targetState.tStates))
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let finalState = RegisterState(machine: machine)
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XCTAssertEqual(finalState, targetState, "Failed \(itemDictionary["name"] as! String)")
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if finalState != targetState {
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failures = failures + 1
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if failures == 5 {
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return
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}
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}
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XCTAssert(finalState == targetState, "Failed \(name)")
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// if finalState != targetState {
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// failures = failures + 1
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// if failures == 5 {
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// return
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// }
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// }
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// TODO compare bus operations and final memory state
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index = index + 1
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}
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}
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}
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@ -133,6 +133,8 @@ struct MicroOp {
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CalculateRSTDestination,
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IndexedPlaceHolder,
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None
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};
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Type type;
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@ -192,6 +194,9 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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#define XX {MicroOp::None, 0}
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#define INDEX() {MicroOp::IndexedPlaceHolder}, FETCH(temp8_, pc_), WAIT(5), {MicroOp::CalculateIndexAddress, &index}
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#define IR_ADDR() (add_offsets ? temp16_ : index)
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/// Fetches into x from address y, and then increments y.
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#define FETCH(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Read, 3, &y.full, &x}}, {MicroOp::Increment16, &y.full}
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/// Fetches into x from address y.
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@ -221,14 +226,14 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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#define LD(a, b) Program({MicroOp::Move8, &b, &a})
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#define LD_GROUP(r) \
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LD(r, bc_.bytes.high), LD(r, bc_.bytes.low), LD(r, de_.bytes.high), LD(r, de_.bytes.low), \
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LD(r, bc_.bytes.high), LD(r, bc_.bytes.low), LD(r, de_.bytes.high), LD(r, de_.bytes.low), \
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LD(r, index.bytes.high), LD(r, index.bytes.low), Program(FETCHL(r, index)), LD(r, a_)
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#define OP_GROUP(op) \
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Program({MicroOp::op, &bc_.bytes.high}), Program({MicroOp::op, &bc_.bytes.low}), \
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Program({MicroOp::op, &de_.bytes.high}), Program({MicroOp::op, &de_.bytes.low}), \
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Program({MicroOp::op, &index.bytes.high}), Program({MicroOp::op, &index.bytes.low}), \
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Program(FETCHL(temp8_, index), {MicroOp::op, &temp8_}), \
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Program(INDEX(), FETCHL(temp8_, IR_ADDR()), {MicroOp::op, &temp8_}), \
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Program({MicroOp::op, &a_})
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#define ADD16(d, s) Program(WAIT(4), WAIT(3), {MicroOp::ADD16, &s.full, &d.full})
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@ -240,7 +245,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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typedef MicroOp InstructionTable[256][20];
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void assemble_page(InstructionPage &target, InstructionTable &table) {
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void assemble_page(InstructionPage &target, InstructionTable &table, bool add_offsets) {
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size_t number_of_micro_ops = 0;
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size_t lengths[256];
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@ -259,9 +264,21 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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// Copy in all programs and set pointers.
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size_t destination = 0;
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for(int c = 0; c < 256; c++) {
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memcpy(&target.all_operations[destination], table[c], lengths[c] * sizeof(MicroOp));
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target.instructions[c] = &target.all_operations[destination];
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destination += lengths[c];
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if(c == 0x86)
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printf("!");
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for(int t = 0; t < lengths[c];) {
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// If an index placeholder is hit then drop it, and if offsets aren't being added,
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// then also drop the indexing that follows and which is assumed here to be four
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// micro-ops in length. Coupled to the INDEX() macro.
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if(table[c][t].type == MicroOp::IndexedPlaceHolder) {
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t++;
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if(!add_offsets) t += 4;
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}
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target.all_operations[destination] = table[c][t];
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destination++;
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t++;
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}
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}
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}
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@ -325,7 +342,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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NOP_ROW(), /* 0xe0 */
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NOP_ROW(), /* 0xf0 */
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};
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assemble_page(target, ed_program_table);
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assemble_page(target, ed_program_table, false);
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#undef NOP_ROW
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}
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@ -389,8 +406,8 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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/* 0x30 JR NC */ JR(TestNC), /* 0x31 LD SP, nn */ Program(FETCH16(sp_, pc_)),
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/* 0x32 LD (nn), A */ Program(FETCH16(temp16_, pc_), STOREL(a_, temp16_)),
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/* 0x33 INC SP */ Program(WAIT(2), {MicroOp::Increment16, &sp_.full}),
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/* 0x34 INC (HL) */ Program(FETCHL(temp8_, hl_), WAIT(1), {MicroOp::Increment8, &temp8_}, STOREL(temp8_, hl_)),
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/* 0x35 DEC (HL) */ Program(FETCHL(temp8_, hl_), WAIT(1), {MicroOp::Decrement8, &temp8_}, STOREL(temp8_, hl_)),
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/* 0x34 INC (HL) */ Program( FETCHL(temp8_, index), WAIT(1), {MicroOp::Increment8, &temp8_}, STOREL(temp8_, index)),
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/* 0x35 DEC (HL) */ Program(FETCHL(temp8_, index), WAIT(1), {MicroOp::Decrement8, &temp8_}, STOREL(temp8_, index)),
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/* 0x36 LD (HL), n */ Program(FETCH(temp8_, pc_), STOREL(temp8_, index)),
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/* 0x37 SCF */ Program({MicroOp::SCF}),
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/* 0x38 JR C */ JR(TestC),
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@ -494,7 +511,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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/* 0xfe CP n */ Program(FETCH(temp8_, pc_), {MicroOp::CP8, &temp8_}),
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/* 0xff RST 38h */ RST(),
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};
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assemble_page(target, base_program_table);
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assemble_page(target, base_program_table, add_offsets);
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}
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void assemble_fetch_decode_execute() {
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@ -523,8 +540,8 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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public:
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Processor() : MicroOpScheduler() {
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assemble_base_page(base_page_, hl_, false);
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assemble_base_page(dd_page_, ix_, false);
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assemble_base_page(fd_page_, iy_, false);
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assemble_base_page(dd_page_, ix_, true);
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assemble_base_page(fd_page_, iy_, true);
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assemble_ed_page(ed_page_);
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assemble_fetch_decode_execute();
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}
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@ -568,7 +585,6 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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if(number_of_cycles_ < operation->machine_cycle.length) { schedule_program_program_counter_--; return; }
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number_of_cycles_ -= operation->machine_cycle.length;
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number_of_cycles_ -= static_cast<T *>(this)->perform_machine_cycle(&operation->machine_cycle);
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if(number_of_cycles_ <= 0) return;
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break;
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case MicroOp::MoveToNextProgram:
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move_to_next_program();
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