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https://github.com/TomHarte/CLK.git
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Ensures unmapped peripherals return a consistent value.
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@ -106,11 +106,16 @@ class ConcreteMachine:
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} else {
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iwm_.write(register_address, cycle.value->halves.low);
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}
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printf("IWM %d %c [%02x]\n", register_address & 0xf, (cycle.operation & Microcycle::Read) ? 'r' : 'w', cycle.value->halves.low);
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// printf("IWM %d %c [%02x]\n", register_address & 0xf, (cycle.operation & Microcycle::Read) ? 'r' : 'w', cycle.value->halves.low);
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break;
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default:
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if(cycle.operation & Microcycle::Read) {
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cycle.value->halves.low = 0xff;
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if(cycle.operation & Microcycle::SelectWord) cycle.value->halves.high = 0xff;
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}
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break;
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}
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// printf("\n");
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}
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} else {
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if(cycle.data_select_active()) {
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@ -217,7 +222,7 @@ class ConcreteMachine:
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b3: 0 = use alternate sound buffer, 1 = use ordinary sound buffer
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b2–b0: audio output volume
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*/
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printf("6522 A: %02x\n", value);
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// printf("6522 A: %02x\n", value);
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machine_.set_rom_is_overlay(!!(value & 0x10));
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machine_.set_use_alternate_screen_buffer(!(value & 0x40));
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break;
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@ -234,7 +239,7 @@ class ConcreteMachine:
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b1: clock's data-clock line
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b0: clock's serial data line
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*/
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printf("6522 B: %02x\n", value);
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// printf("6522 B: %02x\n", value);
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break;
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}
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}
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@ -242,17 +247,17 @@ class ConcreteMachine:
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uint8_t get_port_input(Port port) {
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switch(port) {
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case Port::A:
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printf("6522 r A\n");
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// printf("6522 r A\n");
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return 0xff;
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case Port::B:
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printf("6522 r B\n");
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// printf("6522 r B\n");
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return 0x00;
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}
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}
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void set_control_line_output(Port port, Line line, bool value) {
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printf("6522 line %c%d: %c\n", port ? 'B' : 'A', int(line), value ? 't' : 'f');
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// printf("6522 line %c%d: %c\n", port ? 'B' : 'A', int(line), value ? 't' : 'f');
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}
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private:
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