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mirror of https://github.com/TomHarte/CLK.git synced 2025-01-26 15:32:04 +00:00

Towards ST 1bpp support: puts vsync in an appropriate location, starts experimenting with proper CRT timings.

This commit is contained in:
Thomas Harte 2020-01-27 23:00:30 -05:00
parent 8e094598ca
commit 9d340599a6
6 changed files with 196 additions and 13 deletions

View File

@ -567,7 +567,7 @@ class ConcreteMachine:
GPIP 0: centronics busy
*/
mfp_->set_port_input(
0x80 | // b7: Monochrome monitor detect (1 = is monochrome).
0x00 | // b7: Monochrome monitor detect (0 = is monochrome).
0x40 | // b6: RS-232 ring indicator.
(dma_->get_interrupt_line() ? 0x00 : 0x20) | // b5: FD/HS interrupt (0 = interrupt requested).
((keyboard_acia_->get_interrupt_line() || midi_acia_->get_interrupt_line()) ? 0x00 : 0x10) | // b4: Keyboard/MIDI interrupt (0 = interrupt requested).

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@ -29,7 +29,7 @@ const struct VerticalParams {
} vertical_params[3] = {
{63, 263, 313}, // 47 rather than 63 on early machines.
{34, 234, 263},
{1, 401, 500} // 72 Hz mode: who knows?
{51, 451, 500} // 72 Hz mode: who knows?
};
/// @returns The correct @c VerticalParams for output at @c frequency.
@ -57,13 +57,20 @@ const struct HorizontalParams {
const int set_blank;
const int reset_blank;
const int vertical_decision;
const int length;
} horizontal_params[3] = {
{CYCLE(56), CYCLE(376), CYCLE(450), CYCLE(28), CYCLE(512)},
{CYCLE(52), CYCLE(372), CYCLE(450), CYCLE(24), CYCLE(508)},
{CYCLE(4), CYCLE(164), CYCLE(999), CYCLE(999), CYCLE(224)} // 72Hz mode doesn't set or reset blank.
{CYCLE(56), CYCLE(376), CYCLE(450), CYCLE(28), CYCLE(502), CYCLE(512)},
{CYCLE(52), CYCLE(372), CYCLE(450), CYCLE(24), CYCLE(502), CYCLE(508)},
{CYCLE(4), CYCLE(164), CYCLE(999), CYCLE(999), CYCLE(214), CYCLE(224)} // 72Hz mode doesn't set or reset blank.
};
// Re: 'vertical_decision':
// This is cycle 502 if in 50 or 60 Hz mode; in 70 Hz mode I've put it on cycle 214
// in order to be analogous to 50 and 60 Hz mode. I have no idea where it should
// actually go.
const HorizontalParams &horizontal_parameters(Video::FieldFrequency frequency) {
return horizontal_params[int(frequency)];
}
@ -111,12 +118,13 @@ const int vsync_delay_period = hsync_delay_period; // Signal vsync with the same
Video::Video() :
deferrer_([=] (HalfCycles duration) { advance(duration); }),
crt_(1024, 1, Outputs::Display::Type::PAL50, Outputs::Display::InputDataType::Red4Green4Blue4),
// crt_(1024, 1, Outputs::Display::Type::PAL50, Outputs::Display::InputDataType::Red4Green4Blue4),
crt_(448, 1, 500, Outputs::Display::ColourSpace::YIQ, 100, 50, 5, false, Outputs::Display::InputDataType::Red4Green4Blue4),
video_stream_(crt_, palette_) {
// Show a total of 260 lines; a little short for PAL but a compromise between that and the ST's
// usual output height of 200 lines.
crt_.set_visible_area(crt_.get_rect_for_area(33, 260, 220, 850, 4.0f / 3.0f));
// crt_.set_visible_area(crt_.get_rect_for_area(33, 260, 220, 850, 4.0f / 3.0f));
}
void Video::set_ram(uint16_t *ram, size_t size) {
@ -256,8 +264,8 @@ void Video::advance(HalfCycles duration) {
// Check for whether line length should have been latched during this run.
if(x_ <= CYCLE(54) && (x_ + run_length) > CYCLE(54)) line_length_ = horizontal_timings.length;
// Make a decision about vertical state on cycle 502.
if(x_ <= CYCLE(502) && (x_ + run_length) > CYCLE(502)) {
// Make a decision about vertical state on the appropriate cycle.
if(x_ <= horizontal_timings.vertical_decision && (x_ + run_length) > horizontal_timings.vertical_decision) {
next_y_ = y_ + 1;
next_vertical_ = vertical_;
next_vertical_.sync_schedule = VerticalState::SyncSchedule::None;
@ -761,7 +769,13 @@ void Video::VideoStream::set_bpp(OutputBpp bpp) {
}
void Video::VideoStream::load(uint64_t value) {
output_shifter_ = value;
// In 1bpp mode, a 0 bit is white and a 1 bit is black.
// Invert the input so that the 'just output the border colour
// when the shifter is empty' optimisation works.
if(bpp_ == OutputBpp::One)
output_shifter_ = ~value;
else
output_shifter_ = value;
}
// MARK: - Range observer.

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@ -3858,6 +3858,7 @@
};
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@ -5059,7 +5060,6 @@
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@ -5104,7 +5104,6 @@
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CLANG_WARN__EXIT_TIME_DESTRUCTORS = YES;
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ENABLE_HARDENED_RUNTIME = YES;
@ -5144,7 +5143,10 @@
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CLANG_CXX_LANGUAGE_STANDARD = "c++17";
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CODE_SIGN_ENTITLEMENTS = "Clock Signal/Clock Signal.entitlements";
COMBINE_HIDPI_IMAGES = YES;
DEVELOPMENT_TEAM = CP2SKEB3XT;
ENABLE_HARDENED_RUNTIME = NO;
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LD_RUNPATH_SEARCH_PATHS = "$(inherited) @executable_path/../Frameworks @loader_path/../Frameworks";
PRODUCT_BUNDLE_IDENTIFIER = "TH.Clock-SignalTests";
@ -5162,7 +5164,10 @@
BUNDLE_LOADER = "$(TEST_HOST)";
CLANG_CXX_LANGUAGE_STANDARD = "c++17";
CLANG_ENABLE_MODULES = YES;
CODE_SIGN_ENTITLEMENTS = "Clock Signal/Clock Signal.entitlements";
COMBINE_HIDPI_IMAGES = YES;
DEVELOPMENT_TEAM = CP2SKEB3XT;
ENABLE_HARDENED_RUNTIME = NO;
GCC_OPTIMIZATION_LEVEL = 2;
INFOPLIST_FILE = "Clock SignalTests/Info.plist";
LD_RUNPATH_SEARCH_PATHS = "$(inherited) @executable_path/../Frameworks @loader_path/../Frameworks";

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@ -0,0 +1,93 @@
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@ -67,7 +67,7 @@
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