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mirror of https://github.com/TomHarte/CLK.git synced 2024-09-29 16:55:59 +00:00

Let's try just declining to pump the PLL while in write mode. Added documentation to explain.

This commit is contained in:
Thomas Harte 2016-12-25 09:19:18 -05:00
parent b57038edc5
commit 9d555c4a02
2 changed files with 7 additions and 7 deletions

View File

@ -68,7 +68,7 @@ void Controller::run_for_cycles(int number_of_cycles)
cycles_since_index_hole_ += (unsigned int)cycles_to_run_for;
number_of_cycles -= cycles_to_run_for;
pll_->run_for_cycles(cycles_to_run_for);
if(is_reading_) pll_->run_for_cycles(cycles_to_run_for);
TimedEventLoop::run_for_cycles(cycles_to_run_for);
}
}
@ -97,7 +97,7 @@ void Controller::process_next_event()
switch(current_event_.type)
{
case Track::Event::FluxTransition:
pll_->add_pulse();
if(is_reading_) pll_->add_pulse();
break;
case Track::Event::IndexHole:
printf("%p %d [/%d = %d]\n", this, cycles_since_index_hole_, clock_rate_multiplier_, cycles_since_index_hole_ / clock_rate_multiplier_);

View File

@ -62,9 +62,10 @@ class Controller: public DigitalPhaseLockedLoop::Delegate, public TimedEventLoop
bool get_motor_on();
/*!
Begins write mode, initiating a PCM sampled region of data. During write mode, no events will
be reported. Bits should be written via @c write_bit. They will be written with the length set
via @c set_expected_bit_length.
Begins write mode, initiating a PCM sampled region of data. Bits should be written via
@c write_bit. They will be written with the length set via @c set_expected_bit_length.
It is acceptable to supply a backlog of bits. Flux transition events will not be reported
while writing.
*/
void begin_writing();
@ -74,8 +75,7 @@ class Controller: public DigitalPhaseLockedLoop::Delegate, public TimedEventLoop
void write_bit(bool value);
/*!
Ends write mode, switching back to read mode. The drive will return to posting events based
on the recorded track.
Ends write mode, switching back to read mode. The drive will stop overwriting events.
*/
void end_writing();