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synced 2025-02-26 08:29:33 +00:00
Let's try just declining to pump the PLL while in write mode. Added documentation to explain.
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@ -68,7 +68,7 @@ void Controller::run_for_cycles(int number_of_cycles)
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cycles_since_index_hole_ += (unsigned int)cycles_to_run_for;
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number_of_cycles -= cycles_to_run_for;
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pll_->run_for_cycles(cycles_to_run_for);
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if(is_reading_) pll_->run_for_cycles(cycles_to_run_for);
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TimedEventLoop::run_for_cycles(cycles_to_run_for);
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}
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}
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@ -97,7 +97,7 @@ void Controller::process_next_event()
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switch(current_event_.type)
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{
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case Track::Event::FluxTransition:
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pll_->add_pulse();
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if(is_reading_) pll_->add_pulse();
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break;
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case Track::Event::IndexHole:
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printf("%p %d [/%d = %d]\n", this, cycles_since_index_hole_, clock_rate_multiplier_, cycles_since_index_hole_ / clock_rate_multiplier_);
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@ -62,9 +62,10 @@ class Controller: public DigitalPhaseLockedLoop::Delegate, public TimedEventLoop
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bool get_motor_on();
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/*!
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Begins write mode, initiating a PCM sampled region of data. During write mode, no events will
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be reported. Bits should be written via @c write_bit. They will be written with the length set
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via @c set_expected_bit_length.
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Begins write mode, initiating a PCM sampled region of data. Bits should be written via
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@c write_bit. They will be written with the length set via @c set_expected_bit_length.
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It is acceptable to supply a backlog of bits. Flux transition events will not be reported
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while writing.
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*/
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void begin_writing();
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@ -74,8 +75,7 @@ class Controller: public DigitalPhaseLockedLoop::Delegate, public TimedEventLoop
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void write_bit(bool value);
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/*!
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Ends write mode, switching back to read mode. The drive will return to posting events based
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on the recorded track.
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Ends write mode, switching back to read mode. The drive will stop overwriting events.
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*/
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void end_writing();
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