mirror of
https://github.com/TomHarte/CLK.git
synced 2024-11-25 16:31:42 +00:00
Introduce overlooked: ld, ldu, rldclx, rldcrx, rldicx, rldiclx, rldicrx, rldimix.
This commit is contained in:
Thomas Harte
parent
da0f7d7907
commit
9e0755bc86
@ -209,7 +209,7 @@ template <Model model, bool validate_reserved_bits, Operation operation> Instruc
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case Operation::lhz: case Operation::lhzu:
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case Operation::lmw: case Operation::lwa:
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case Operation::lwz: case Operation::lwzu:
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case Operation::mulld: case Operation::mulli: case Operation::mullwx:
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case Operation::mulldx: case Operation::mulli: case Operation::mullwx:
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case Operation::nandx: case Operation::norx:
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case Operation::orx: case Operation::orcx:
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case Operation::ori: case Operation::oris:
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@ -229,9 +229,10 @@ template <Model model, bool validate_reserved_bits, Operation operation> Instruc
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case Operation::subfic:
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case Operation::tdi: case Operation::twi:
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case Operation::xorx: case Operation::xori: case Operation::xoris:
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// TODO: ld ldu
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// TODO: rldclx rldcrx rldicx rldicrx rldimix
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case Operation::ld: case Operation::ldu:
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case Operation::rldclx: case Operation::rldcrx:
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case Operation::rldicx: case Operation::rldiclx:
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case Operation::rldicrx: case Operation::rldimix:
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break;
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}
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@ -341,7 +342,7 @@ Instruction Decoder<model, validate_reserved_bits>::decode(uint32_t opcode) {
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BindConditional(is64bit, SixTen(0b011111, 0b0001010100), ldarx);
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BindConditional(is64bit, SixTen(0b011111, 0b0010010101), stdx);
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BindConditional(is64bit, SixTen(0b011111, 0b0010110101), stdux);
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BindConditional(is64bit, SixTen(0b011111, 0b0011101001), mulld); BindConditional(is64bit, SixTen(0b011111, 0b1011101001), mulld);
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BindConditional(is64bit, SixTen(0b011111, 0b0011101001), mulldx); BindConditional(is64bit, SixTen(0b011111, 0b1011101001), mulldx);
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BindConditional(is64bit, SixTen(0b011111, 0b0101010101), lwax);
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BindConditional(is64bit, SixTen(0b011111, 0b0101110101), lwaux);
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BindConditional(is64bit, SixTen(0b011111, 0b1100111011), sradix); BindConditional(is64bit, SixTen(0b011111, 0b1100111010), sradix);
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@ -539,6 +540,8 @@ Instruction Decoder<model, validate_reserved_bits>::decode(uint32_t opcode) {
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BindConditional(is64bit, SixTen(0b111011, 0b10110), fsqrtsx);
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BindConditional(is64bit, SixTen(0b111011, 0b11000), fresx);
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BindConditional(is64bit, SixTen(0b011110, 0b01000), rldclx);
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BindConditional(is64bit, SixTen(0b011110, 0b01001), rldcrx);
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// Optional...
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Bind(SixTen(0b111111, 0b10110), fsqrtx);
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@ -546,23 +549,36 @@ Instruction Decoder<model, validate_reserved_bits>::decode(uint32_t opcode) {
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Bind(SixTen(0b111111, 0b11010), frsqrtex);
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}
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// rldicx, rldiclx, rldicrx, rldimix
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if(is64bit(model)) {
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switch(opcode & 0b111111'00000'00000'00000'000000'111'00) {
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default: break;
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case 0b011110'00000'00000'00000'000000'000'00: return instruction<model, validate_reserved_bits, Operation::rldiclx>(opcode);
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case 0b011110'00000'00000'00000'000000'001'00: return instruction<model, validate_reserved_bits, Operation::rldicrx>(opcode);
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case 0b011110'00000'00000'00000'000000'010'00: return instruction<model, validate_reserved_bits, Operation::rldicx>(opcode);
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case 0b011110'00000'00000'00000'000000'011'00: return instruction<model, validate_reserved_bits, Operation::rldimix>(opcode);
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}
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}
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// stwcx. and stdcx.
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switch(opcode & 0b111111'0000'0000'0000'0000'111111111'1) {
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default: break;
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case 0b011111'0000'0000'0000'0000'010010110'1: return instruction<model, validate_reserved_bits, Operation::stwcx_>(opcode);
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case 0b011111'0000'0000'0000'0000'011010110'1:
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if(is64bit(model)) return instruction<model, validate_reserved_bits, Operation::stdcx_>(opcode);
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return Instruction(opcode);
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}
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// std and stdu [TODO: or ld and ldu?]
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switch(opcode & 0b111111'00'00000000'00000000'000000'11) {
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case 0b111110'00'00000000'00000000'000000'00: return instruction<model, validate_reserved_bits, Operation::std>(opcode);
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case 0b111110'00'00000000'00000000'000000'01:
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if(is64bit(model)) return instruction<model, validate_reserved_bits, Operation::stdu>(opcode);
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return Instruction(opcode);
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case 0b111010'00'00000000'00000000'000000'10:
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if(is64bit(model)) return instruction<model, validate_reserved_bits, Operation::lwa>(opcode);
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return Instruction(opcode);
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// std, stdu, ld, ldu, lwa
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if(is64bit(model)) {
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switch(opcode & 0b111111'00'00000000'00000000'000000'11) {
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default: break;
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case 0b111010'00'00000000'00000000'000000'00: return instruction<model, validate_reserved_bits, Operation::ld>(opcode);
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case 0b111010'00'00000000'00000000'000000'01: return instruction<model, validate_reserved_bits, Operation::ldu>(opcode);
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case 0b111010'00'00000000'00000000'000000'10: return instruction<model, validate_reserved_bits, Operation::lwa>(opcode);
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case 0b111110'00'00000000'00000000'000000'00: return instruction<model, validate_reserved_bits, Operation::std>(opcode);
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case 0b111110'00'00000000'00000000'000000'01: return instruction<model, validate_reserved_bits, Operation::stdu>(opcode);
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}
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}
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// sc
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@ -219,6 +219,11 @@ enum class Operation: uint8_t {
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// MARK: - 32- and 64-bit PowerPC instructions.
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//
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/// Add.
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/// add add. addo addo.
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/// rD(), rA(), rB() [rc(), oe()]
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addx,
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/// Add carrying.
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/// addc addc. addco addco.
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/// rD(), rA(), rB() [rc(), oe()]
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@ -254,16 +259,16 @@ enum class Operation: uint8_t {
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/// rD(), rA() [rc(), oe()]
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addmex,
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/// Add.
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/// add add. addo addo.
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/// rD(), rA(), rB() [rc(), oe()]
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addx,
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/// Add to zero extended.
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/// addze addze. addzeo addzeo.
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/// rD(), rA() [rc(), oe()]
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addzex,
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/// And.
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/// and, and.
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/// rA(), rS(), rB() [rc()]
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andx,
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/// And with complement.
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/// andc, andc.
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/// rA(), rS(), rB() [rc()]
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@ -279,10 +284,10 @@ enum class Operation: uint8_t {
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/// rA(), rS(), uimm()
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andis_,
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/// And.
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/// and, and.
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/// rA(), rS(), rB() [rc()]
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andx,
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/// Branch unconditional.
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/// b bl ba bla
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/// li() [aa(), lk()]
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bx,
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/// Branch conditional.
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/// bne bne+ beq bdnzt+ bdnzf bdnzt bdnzfla ...
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@ -299,11 +304,6 @@ enum class Operation: uint8_t {
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/// bo(), bi() [aa(), lk()]
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bclrx,
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/// Branch unconditional.
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/// b bl ba bla
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/// li() [aa(), lk()]
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bx,
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/// Compare
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/// cmp
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/// crfD(), l(), rA(), rB()
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@ -394,16 +394,16 @@ enum class Operation: uint8_t {
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/// rA(), rB()
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dcbz,
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/// Divide word unsigned.
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/// divwu divwu. divwuo divwuo.
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/// rD(), rA(), rB() [rc(), oe()]
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divwux,
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/// Divide word.
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/// divw divw. divwo divwo.
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/// rD(), rA(), rB() [rc(), oe()]
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divwx,
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/// Divide word unsigned.
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/// divwu divwu. divwuo divwuo.
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/// rD(), rA(), rB() [rc(), oe()]
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divwux,
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/// External control in word indexed.
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/// eciwx
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/// rD(), rA(), rB()
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@ -438,16 +438,16 @@ enum class Operation: uint8_t {
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/// frD(), frB() [rc()]
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fabsx,
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/// Floating point add single precision.
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/// fadds fadds.
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/// frD(), frA(), frB() [rc()]
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faddsx,
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/// Floating point add.
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/// fadd fadd.
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/// frD(), frA(), frB() [rc()]
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faddx,
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/// Floating point add single precision.
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/// fadds fadds.
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/// frD(), frA(), frB() [rc()]
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faddsx,
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/// Floating point compare ordered.
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/// fcmpo
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/// crfD(), frA(), frB()
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@ -468,51 +468,51 @@ enum class Operation: uint8_t {
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/// frD(), frB() [rc()]
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fctiwzx,
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/// Floating point divide single precision.
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/// fdiv fdiv.
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/// frD(), frA(), frB() [rc()]
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fdivsx,
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/// Floating point divide.
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/// fdiv fdiv.
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/// frD(), frA(), frB() [rc()]
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fdivx,
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/// Floating point multiply add single precision.
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/// fmadds fmadds.
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/// frD(), frA(), frC(), frB() [rc()]
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fmaddsx,
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/// Floating point divide single precision.
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/// fdiv fdiv.
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/// frD(), frA(), frB() [rc()]
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fdivsx,
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/// Floating point multiply add.
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/// fmadd fmadd.
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/// frD(), frA(), frC(), frB() [rc()]
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fmaddx,
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/// Floating point multiply add single precision.
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/// fmadds fmadds.
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/// frD(), frA(), frC(), frB() [rc()]
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fmaddsx,
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/// Floating point register move.
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/// fmr fmr.
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/// frD(), frB() [rc()]
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fmrx,
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/// Floating point multiply subtract single precision.
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/// fmsubx fmsubx.
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/// frD(), frA(), frC(), frB() [rc()]
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fmsubsx,
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/// Floating point multiply subtract.
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/// fmsub fmsub.
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/// frD(), frA(), frC(), frB() [rc()]
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fmsubx,
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/// Floating point multiply single precision.
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/// fmuls fmuls.
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/// frD(), frA(), frC() [rc()]
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fmulsx,
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/// Floating point multiply subtract single precision.
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/// fmsubx fmsubx.
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/// frD(), frA(), frC(), frB() [rc()]
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fmsubsx,
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/// Floating point multiply.
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/// fmul fmul.
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/// frD(), frA(), frC() [rc()]
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fmulx,
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/// Floating point multiply single precision.
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/// fmuls fmuls.
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/// frD(), frA(), frC() [rc()]
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fmulsx,
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/// Floating negative absolute value.
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/// fnabs fnabs.
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/// frD(), frB() [rc()]
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@ -523,41 +523,41 @@ enum class Operation: uint8_t {
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/// frD(), frB() [rc()]
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fnegx,
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/// Floating point negative multiply add single precision.
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/// fnmadds fnmadds.
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/// frD(), frA(), frC(), frB() [rc()]
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fnmaddsx,
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/// Floating point negative multiply add.
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/// fnmadd fnmadd.
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/// frD(), frA(), frC(), frB() [rc()]
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fnmaddx,
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/// Floating point negative multiply add.
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/// fnmsubs fnmsubs.
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/// Floating point negative multiply add single precision.
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/// fnmadds fnmadds.
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/// frD(), frA(), frC(), frB() [rc()]
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fnmsubsx,
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fnmaddsx,
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/// Floating point negative multiply subtract.
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/// fnmsub fnmsub.
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/// frD(), frA(), frC(), frB() [rc()]
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fnmsubx,
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/// Floating point negative multiply add.
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/// fnmsubs fnmsubs.
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/// frD(), frA(), frC(), frB() [rc()]
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fnmsubsx,
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/// Floating point round to single precision.
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/// frsp frsp.
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/// frD(), frB() [rc()]
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frspx,
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/// Floating point subtract single precision.
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/// fsubs fsubs.
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/// frD(), frA(), frB() [rc()]
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fsubsx,
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/// Floating point subtract.
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/// fsub fsub.
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/// frD(), frA(), frB() [rc()]
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fsubx,
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/// Floating point subtract single precision.
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/// fsubs fsubs.
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/// frD(), frA(), frB() [rc()]
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fsubsx,
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/// Instruction cache block invalidate.
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/// icbi
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/// rA(), rB()
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@ -840,6 +840,11 @@ enum class Operation: uint8_t {
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/// rA(), rS(), rB() [rc()]
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norx,
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/// OR.
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/// or or.
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/// rA(), rS(), rB() [rc()]
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orx,
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/// OR with complement.
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/// orc orc.
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/// rA(), rS(), rB() [rc()]
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@ -855,11 +860,6 @@ enum class Operation: uint8_t {
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/// rA(), rS(), uimm()
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oris,
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/// OR.
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/// or or.
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/// rA(), rS(), rB() [rc()]
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orx,
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/// Return from interrupt.
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/// rfi
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rfi,
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@ -888,21 +888,26 @@ enum class Operation: uint8_t {
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/// rA(), rS(), rB() [rc()]
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slwx,
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/// Shift right algebraic word immediate.
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/// srawi srawi.
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/// rA(), rS(), sh() [rc()]
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srawix,
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/// Shift right algebraic word.
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/// sraw sraw.
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/// rA(), rS(), rB() [rc()]
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srawx,
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/// Shift right algebraic word immediate.
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/// srawi srawi.
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/// rA(), rS(), sh() [rc()]
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srawix,
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/// Shift right word.
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/// srw srw.
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/// rA(), rS(), rB() [rc()]
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srwx,
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/// Store byte indexed.
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/// stbx
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/// rS(), rA(), rB()
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stbx,
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/// Store byte.
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/// stb
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/// rS(), d() [ rA() ]
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@ -918,11 +923,6 @@ enum class Operation: uint8_t {
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/// rS(), rA(), rB()
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stbux,
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/// Store byte indexed.
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/// stbx
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/// rS(), rA(), rB()
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stbx,
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/// Store floating point double precision.
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/// stfd
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/// frS(), d() [ rA() ]
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@ -1033,6 +1033,11 @@ enum class Operation: uint8_t {
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/// rS(), rA(), rB()
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stwx,
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/// Subtract from.
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/// subf subf. subfo subfo.
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/// rD(), rA(), rB() [rc(), oe()]
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subfx,
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/// Subtract from carrying.
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/// subfc subfc. subfco subfco.
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/// rD(), rA(), rB() [rc(), oe()]
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@ -1053,11 +1058,6 @@ enum class Operation: uint8_t {
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/// rD(), rA() [rc(), oe()]
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subfmex,
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/// Subtract from.
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/// subf subf. subfo subfo.
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/// rD(), rA(), rB() [rc(), oe()]
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subfx,
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/// Subtract from zero extended.
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/// subfze subfze. subfzeo subfzeo.
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/// rD(), rA() [rc(), oe()]
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@ -1077,6 +1077,11 @@ enum class Operation: uint8_t {
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/// to(), rA(), simm()
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twi,
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/// Xor.
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/// xor xor.
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/// rA(), rS(), rB() [rc()]
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xorx,
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/// Xor immediate.
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/// xori
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/// rA(), rs(), uimm()
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@ -1087,11 +1092,6 @@ enum class Operation: uint8_t {
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/// rA(), rS(), uimm()
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xoris,
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/// Xor.
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/// xor xor.
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/// rA(), rS(), rB() [rc()]
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xorx,
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//
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// MARK: - 32-bit, supervisor level.
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//
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@ -1142,16 +1142,16 @@ enum class Operation: uint8_t {
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/// frD(), frA(), frC(), frB() [rc()]
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fselx,
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/// Floating point square root single precision.
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/// fsqrts fsqrts.
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/// frD(), frB() [rc()]
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fsqrtsx,
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/// Floating Point square root.
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/// fsqrt fsqrt.
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/// frD(), frB() [rc()]
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fsqrtx,
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/// Floating point square root single precision.
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/// fsqrts fsqrts.
|
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/// frD(), frB() [rc()]
|
||||
fsqrtsx,
|
||||
|
||||
/// Store floating point as integer word indexed.
|
||||
/// stfiwx
|
||||
/// frS(), rA(), rB()
|
||||
@ -1166,16 +1166,16 @@ enum class Operation: uint8_t {
|
||||
/// rA(), rS() [rc()]
|
||||
cntlzdx,
|
||||
|
||||
/// Divide double word unsigned.
|
||||
/// divdu divdu. divduo divduo.
|
||||
/// rD(), rA(), rB() [rc(), oe()]
|
||||
divdux,
|
||||
|
||||
/// Divide double word.
|
||||
/// divd divd. divdo divdo.
|
||||
/// rD(), rA(), rB() [rc(), oe()]
|
||||
divdx,
|
||||
|
||||
/// Divide double word unsigned.
|
||||
/// divdu divdu. divduo divduo.
|
||||
/// rD(), rA(), rB() [rc(), oe()]
|
||||
divdux,
|
||||
|
||||
/// Extend sign word.
|
||||
/// extsw extsw.
|
||||
/// rA(), rS() [rc()]
|
||||
@ -1196,11 +1196,17 @@ enum class Operation: uint8_t {
|
||||
/// frD(), frB() [rc()]
|
||||
fctidzx,
|
||||
|
||||
/// TODO
|
||||
ld,
|
||||
|
||||
/// Load double word and reserve indezed.
|
||||
/// ldarx
|
||||
/// rD(), rA(), rB()
|
||||
ldarx,
|
||||
|
||||
/// TODO
|
||||
ldu,
|
||||
|
||||
/// Load double word with update indexed.
|
||||
/// ldux
|
||||
/// frD(), rA(), rB()
|
||||
@ -1226,20 +1232,38 @@ enum class Operation: uint8_t {
|
||||
/// rD(), rA(), rB()
|
||||
lwax,
|
||||
|
||||
/// Multiply high double word unsigned.
|
||||
/// mulhdy mulhdu.
|
||||
/// rD(), rA(), rB() [rc()]
|
||||
mulhdux,
|
||||
|
||||
/// Multiply high double word.
|
||||
/// mulhd mulhd.
|
||||
/// rD(), rA(), rB() [rc()]
|
||||
mulhdx,
|
||||
|
||||
/// Multiply high double word unsigned.
|
||||
/// mulhdy mulhdu.
|
||||
/// rD(), rA(), rB() [rc()]
|
||||
mulhdux,
|
||||
|
||||
/// Multiply low double word.
|
||||
/// mulld mulld. mulldo mulldo.
|
||||
/// rD(), rA(), rB() [rc()]
|
||||
mulld,
|
||||
mulldx,
|
||||
|
||||
/// TODO
|
||||
rldclx,
|
||||
|
||||
/// TODO
|
||||
rldcrx,
|
||||
|
||||
/// TODO
|
||||
rldicx,
|
||||
|
||||
/// TODO
|
||||
rldiclx,
|
||||
|
||||
/// TODO
|
||||
rldicrx,
|
||||
|
||||
/// TODO
|
||||
rldimix,
|
||||
|
||||
/// Segment lookaside buffer ('SLB') invalidate all.
|
||||
/// slbia
|
||||
@ -1255,16 +1279,16 @@ enum class Operation: uint8_t {
|
||||
/// rA(), rS(), rB()
|
||||
sldx,
|
||||
|
||||
/// Shift right algebraic double word immediate.
|
||||
/// sradi sradi.
|
||||
/// rA(), rS(),sh() [rc()]
|
||||
sradix,
|
||||
|
||||
/// Shift right algebraic double word.
|
||||
/// srad srad,
|
||||
/// rA(), rS(), rB() [rc()]
|
||||
sradx,
|
||||
|
||||
/// Shift right algebraic double word immediate.
|
||||
/// sradi sradi.
|
||||
/// rA(), rS(),sh() [rc()]
|
||||
sradix,
|
||||
|
||||
/// Shift right double word.
|
||||
/// srd srd.
|
||||
/// rA(), rS(), rB() [rc()]
|
||||
@ -1383,6 +1407,8 @@ struct Instruction {
|
||||
/// Branch displacement; provided as already sign extended.
|
||||
int16_t bd() const { return int16_t(opcode & 0xfffc); }
|
||||
|
||||
// TODO: both MB/ME and mb/me fields seem to be defined. Investigate.
|
||||
|
||||
/// Specifies the first 1 bit of a 32/64-bit mask for rotate operations.
|
||||
uint32_t mb() const { return (opcode >> 6) & 0x1f; }
|
||||
/// Specifies the first 1 bit of a 32/64-bit mask for rotate operations.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user