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Eliminate potential future implicit conversion warnings.

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This commit is contained in:
Thomas Harte 2022-05-24 11:05:24 -04:00
parent 3349bcaaed
commit 9e3c2b68d7
2 changed files with 38 additions and 38 deletions
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20
InstructionSets/M68k/Implementation/PerformImplementation.hpp
View File

@ -228,7 +228,7 @@ template <
status.zero_result = dest.l & bit_mask; status.zero_result = dest.l & bit_mask;
dest.l &= ~bit_mask; dest.l &= ~bit_mask;
flow_controller.did_bit_op(bit_position); flow_controller.did_bit_op(int(bit_position));
} break; } break;
case Operation::BCHG: { case Operation::BCHG: {
@ -236,7 +236,7 @@ template <
status.zero_result = dest.l & bit_mask; status.zero_result = dest.l & bit_mask;
dest.l ^= bit_mask; dest.l ^= bit_mask;
flow_controller.did_bit_op(bit_position); flow_controller.did_bit_op(int(bit_position));
} break; } break;
case Operation::BSET: { case Operation::BSET: {
@ -244,7 +244,7 @@ template <
status.zero_result = dest.l & bit_mask; status.zero_result = dest.l & bit_mask;
dest.l |= bit_mask; dest.l |= bit_mask;
flow_controller.did_bit_op(bit_position); flow_controller.did_bit_op(int(bit_position));
} break; } break;
#undef get_mask #undef get_mask
@ -252,26 +252,26 @@ template <
case Operation::Bccb: case Operation::Bccb:
flow_controller.template complete_bcc<int8_t>( flow_controller.template complete_bcc<int8_t>(
status.evaluate_condition(instruction.condition()), status.evaluate_condition(instruction.condition()),
src.b); int8_t(src.b));
break; break;
case Operation::Bccw: case Operation::Bccw:
flow_controller.template complete_bcc<int16_t>( flow_controller.template complete_bcc<int16_t>(
status.evaluate_condition(instruction.condition()), status.evaluate_condition(instruction.condition()),
src.w); int16_t(src.w));
break; break;
case Operation::Bccl: case Operation::Bccl:
flow_controller.template complete_bcc<int32_t>( flow_controller.template complete_bcc<int32_t>(
status.evaluate_condition(instruction.condition()), status.evaluate_condition(instruction.condition()),
src.l); int32_t(src.l));
break; break;
case Operation::BSRb: case Operation::BSRb:
flow_controller.bsr(int8_t(src.b)); flow_controller.bsr(uint32_t(int8_t(src.b)));
break; break;
case Operation::BSRw: case Operation::BSRw:
flow_controller.bsr(int16_t(src.w)); flow_controller.bsr(uint32_t(int16_t(src.w)));
break; break;
case Operation::BSRl: case Operation::BSRl:
flow_controller.bsr(src.l); flow_controller.bsr(src.l);
@ -555,7 +555,7 @@ template <
// TRAP, which is a nicer form of ILLEGAL. // TRAP, which is a nicer form of ILLEGAL.
case Operation::TRAP: case Operation::TRAP:
flow_controller.template raise_exception<false>(src.l + Exception::TrapBase); flow_controller.template raise_exception<false>(int(src.l + Exception::TrapBase));
break; break;
case Operation::TRAPV: { case Operation::TRAPV: {
@ -680,7 +680,7 @@ template <
*/ */
case Operation::LINKw: case Operation::LINKw:
flow_controller.link(instruction, int16_t(dest.w)); flow_controller.link(instruction, uint32_t(int16_t(dest.w)));
break; break;
case Operation::UNLINK: case Operation::UNLINK:

56
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
View File

@ -404,7 +404,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord); SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
SetDataAddress(temporary_address_.l); SetDataAddress(temporary_address_.l);
temporary_address_.l = exception_vector_ << 2; temporary_address_.l = uint32_t(exception_vector_ << 2);
Access(program_counter_.high); // nV Access(program_counter_.high); // nV
temporary_address_.l += 2; temporary_address_.l += 2;
@ -436,14 +436,14 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(captured_status_); // ns Access(captured_status_); // ns
// Do the interrupt cycle, to obtain a vector. // Do the interrupt cycle, to obtain a vector.
temporary_address_.l = captured_interrupt_level_; temporary_address_.l = uint32_t(captured_interrupt_level_);
SetupDataAccess(0, Microcycle::InterruptAcknowledge); SetupDataAccess(0, Microcycle::InterruptAcknowledge);
SetDataAddress(temporary_address_.l); SetDataAddress(temporary_address_.l);
Access(temporary_value_.low); // ni Access(temporary_value_.low); // ni
// If VPA is set, autovector. // If VPA is set, autovector.
if(vpa_) { if(vpa_) {
temporary_value_.w = InstructionSet::M68k::Exception::InterruptAutovectorBase - 1 + captured_interrupt_level_; temporary_value_.w = uint16_t(InstructionSet::M68k::Exception::InterruptAutovectorBase - 1 + captured_interrupt_level_);
} }
IdleBus(3); // n- n IdleBus(3); // n- n
@ -1111,7 +1111,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(FetchAddressRegisterIndirectWithDisplacement_bw): BeginState(FetchAddressRegisterIndirectWithDisplacement_bw):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
registers_[8 + instruction_.reg(next_operand_)].l + registers_[8 + instruction_.reg(next_operand_)].l +
int16_t(prefetch_.w); uint32_t(int16_t(prefetch_.w));
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
Prefetch(); // np Prefetch(); // np
@ -1121,7 +1121,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(FetchAddressRegisterIndirectWithDisplacement_l): BeginState(FetchAddressRegisterIndirectWithDisplacement_l):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
registers_[8 + instruction_.reg(next_operand_)].l + registers_[8 + instruction_.reg(next_operand_)].l +
int16_t(prefetch_.w); uint32_t(int16_t(prefetch_.w));
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
Prefetch(); // np Prefetch(); // np
@ -1133,14 +1133,14 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(CalcAddressRegisterIndirectWithDisplacement): BeginState(CalcAddressRegisterIndirectWithDisplacement):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
registers_[8 + instruction_.reg(next_operand_)].l + registers_[8 + instruction_.reg(next_operand_)].l +
int16_t(prefetch_.w); uint32_t(int16_t(prefetch_.w));
Prefetch(); // np Prefetch(); // np
MoveToStateDynamic(post_ea_state_); MoveToStateDynamic(post_ea_state_);
BeginState(JSRJMPAddressRegisterIndirectWithDisplacement): BeginState(JSRJMPAddressRegisterIndirectWithDisplacement):
effective_address_[0].l = effective_address_[0].l =
registers_[8 + instruction_.reg(next_operand_)].l + registers_[8 + instruction_.reg(next_operand_)].l +
int16_t(prefetch_.w); uint32_t(int16_t(prefetch_.w));
IdleBus(1); // n IdleBus(1); // n
temporary_address_.l = instruction_address_.l + 4; temporary_address_.l = instruction_address_.l + 4;
MoveToStateDynamic(post_ea_state_); MoveToStateDynamic(post_ea_state_);
@ -1151,7 +1151,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(FetchProgramCounterIndirectWithDisplacement_bw): BeginState(FetchProgramCounterIndirectWithDisplacement_bw):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
program_counter_.l - 2 + program_counter_.l - 2 +
int16_t(prefetch_.w); uint32_t(int16_t(prefetch_.w));
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
Prefetch(); // np Prefetch(); // np
@ -1161,7 +1161,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(FetchProgramCounterIndirectWithDisplacement_l): BeginState(FetchProgramCounterIndirectWithDisplacement_l):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
program_counter_.l - 2 + program_counter_.l - 2 +
int16_t(prefetch_.w); uint32_t(int16_t(prefetch_.w));
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
Prefetch(); // np Prefetch(); // np
@ -1173,14 +1173,14 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(CalcProgramCounterIndirectWithDisplacement): BeginState(CalcProgramCounterIndirectWithDisplacement):
effective_address_[next_operand_].l = effective_address_[next_operand_].l =
program_counter_.l - 2 + program_counter_.l - 2 +
int16_t(prefetch_.w); uint32_t(int16_t(prefetch_.w));
Prefetch(); // np Prefetch(); // np
MoveToStateDynamic(post_ea_state_); MoveToStateDynamic(post_ea_state_);
BeginState(JSRJMPProgramCounterIndirectWithDisplacement): BeginState(JSRJMPProgramCounterIndirectWithDisplacement):
effective_address_[0].l = effective_address_[0].l =
program_counter_.l - 2 + program_counter_.l - 2 +
int16_t(prefetch_.w); uint32_t(int16_t(prefetch_.w));
IdleBus(1); // n IdleBus(1); // n
temporary_address_.l = instruction_address_.l + 4; temporary_address_.l = instruction_address_.l + 4;
MoveToStateDynamic(post_ea_state_); MoveToStateDynamic(post_ea_state_);
@ -1188,12 +1188,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
// AddressRegisterIndirectWithIndex8bitDisplacement // AddressRegisterIndirectWithIndex8bitDisplacement
// //
#define d8Xn(base) \ #define d8Xn(base) \
base + \ base + \
((prefetch_.w & 0x800) ? \ ((prefetch_.w & 0x800) ? \
registers_[prefetch_.w >> 12].l : \ registers_[prefetch_.w >> 12].l : \
int16_t(registers_[prefetch_.w >> 12].w)) + \ uint32_t(int16_t(registers_[prefetch_.w >> 12].w))) + \
int8_t(prefetch_.b); uint32_t(int8_t(prefetch_.b));
BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw): BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw):
effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l); effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
@ -1268,7 +1268,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// AbsoluteShort // AbsoluteShort
// //
BeginState(FetchAbsoluteShort_bw): BeginState(FetchAbsoluteShort_bw):
effective_address_[next_operand_].l = int16_t(prefetch_.w); effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w));
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
Prefetch(); // np Prefetch(); // np
@ -1276,7 +1276,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
MoveToNextOperand(FetchOperand_bw); MoveToNextOperand(FetchOperand_bw);
BeginState(FetchAbsoluteShort_l): BeginState(FetchAbsoluteShort_l):
effective_address_[next_operand_].l = int16_t(prefetch_.w); effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w));
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);
Prefetch(); // np Prefetch(); // np
@ -1286,12 +1286,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
MoveToNextOperand(FetchOperand_l); MoveToNextOperand(FetchOperand_l);
BeginState(CalcAbsoluteShort): BeginState(CalcAbsoluteShort):
effective_address_[next_operand_].l = int16_t(prefetch_.w); effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w));
Prefetch(); // np Prefetch(); // np
MoveToStateDynamic(post_ea_state_); MoveToStateDynamic(post_ea_state_);
BeginState(JSRJMPAbsoluteShort): BeginState(JSRJMPAbsoluteShort):
effective_address_[0].l = int16_t(prefetch_.w); effective_address_[0].l = uint32_t(int16_t(prefetch_.w));
IdleBus(1); // n IdleBus(1); // n
temporary_address_.l = instruction_address_.l + 4; temporary_address_.l = instruction_address_.l + 4;
MoveToStateDynamic(post_ea_state_); MoveToStateDynamic(post_ea_state_);
@ -1630,7 +1630,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
BeginState(DBcc): BeginState(DBcc):
operand_[0] = registers_[instruction_.reg(0)]; operand_[0] = registers_[instruction_.reg(0)];
operand_[1].w = uint32_t(int16_t(prefetch_.w)); operand_[1].w = uint16_t(int16_t(prefetch_.w));
PerformSpecific(DBcc); PerformSpecific(DBcc);
registers_[instruction_.reg(0)].w = operand_[0].w; registers_[instruction_.reg(0)].w = operand_[0].w;
@ -1831,19 +1831,19 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Prefetch(); // np Prefetch(); // np
Access(temporary_value_.low); // nR Access(temporary_value_.low); // nR
registers_[instruction_.reg(1)].l = temporary_value_.b << 24; registers_[instruction_.reg(1)].l = uint32_t(temporary_value_.b << 24);
temporary_address_.l += 2; temporary_address_.l += 2;
Access(temporary_value_.low); // nR Access(temporary_value_.low); // nR
registers_[instruction_.reg(1)].l |= temporary_value_.b << 16; registers_[instruction_.reg(1)].l |= uint32_t(temporary_value_.b << 16);
temporary_address_.l += 2; temporary_address_.l += 2;
Access(temporary_value_.low); // nr Access(temporary_value_.low); // nr
registers_[instruction_.reg(1)].l |= temporary_value_.b << 8; registers_[instruction_.reg(1)].l |= uint32_t(temporary_value_.b << 8);
temporary_address_.l += 2; temporary_address_.l += 2;
Access(temporary_value_.low); // nr Access(temporary_value_.low); // nr
registers_[instruction_.reg(1)].l |= temporary_value_.b; registers_[instruction_.reg(1)].l |= uint32_t(temporary_value_.b);
Prefetch(); // np Prefetch(); // np
MoveToStateSpecific(Decode); MoveToStateSpecific(Decode);
@ -1856,11 +1856,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Prefetch(); // np Prefetch(); // np
Access(temporary_value_.low); // nR Access(temporary_value_.low); // nR
registers_[instruction_.reg(1)].w = temporary_value_.b << 8; registers_[instruction_.reg(1)].w = uint16_t(temporary_value_.b << 8);
temporary_address_.l += 2; temporary_address_.l += 2;
Access(temporary_value_.low); // nr Access(temporary_value_.low); // nr
registers_[instruction_.reg(1)].w |= temporary_value_.b; registers_[instruction_.reg(1)].w |= uint16_t(temporary_value_.b);
Prefetch(); // np Prefetch(); // np
MoveToStateSpecific(Decode); MoveToStateSpecific(Decode);