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Fix MOV as unconditional branch.
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7cdceb7b4f
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@ -184,10 +184,8 @@ struct Executor {
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// processor mode."
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// processor mode."
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if(fields.destination() == 15) {
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if(fields.destination() == 15) {
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if constexpr (is_comparison(flags.operation())) {
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registers_.set_status(conditions);
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registers_.set_status(conditions);
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if constexpr (!is_comparison(flags.operation())) {
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} else {
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registers_.set_status(pc_proxy);
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registers_.set_pc(pc_proxy);
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registers_.set_pc(pc_proxy);
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}
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}
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} else {
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} else {
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@ -201,7 +199,7 @@ struct Executor {
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}
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}
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} else {
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} else {
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// "If the S flag is clear when Rd is R15, only the 24 PC bits of R15 will be written."
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// "If the S flag is clear when Rd is R15, only the 24 PC bits of R15 will be written."
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if(fields.destination() == 15 && !is_logical(flags.operation())) {
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if(fields.destination() == 15 && !is_comparison(flags.operation())) {
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registers_.set_pc(pc_proxy);
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registers_.set_pc(pc_proxy);
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}
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}
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}
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}
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@ -572,7 +572,7 @@ class ConcreteMachine:
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// static bool log = false;
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// static bool log = false;
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// if(log) {
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// if(log) {
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// logger.info().append("%08x: %08x", executor_.pc(), instruction);
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// logger.info().append("%08x: %08x [r14:%08x]", executor_.pc(), instruction, executor_.registers()[14]);
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// }
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// }
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InstructionSet::ARM::execute<arm_model>(instruction, executor_);
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InstructionSet::ARM::execute<arm_model>(instruction, executor_);
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}
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}
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